User’s Manual
`
`HOW TO USE DDR SDRAM
`
`Document No. E0234E30 (Ver.3.0)
`Date Published April 2002 (K) Japan
`URL: http://www.elpida.com
`
`© Elpida Memory, Inc. 2002
`Petitioner Lenovo (United States) Inc. - Ex. 1012
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`INTRODUCTION
`
`This manual is intended for users who design application systems using double data rate synchronous
`DRAM (DDR SDRAM). Readers of this manual are required to have general knowledge in the fields of
`electrical engineering, logic circuits, as well as detailed knowledge of the functions and usage of
`conventional synchronous DRAM (SDRAM).
`
`Purpose
`
`This manual is intended to give users understanding of basic functions and usage of DDR SDRAM.
`For details about the functions of individual products, refer to the corresponding data sheet. Since
`operation examples that appear in this manual are strictly illustrative, numerical values that appear are
`not guaranteed values. Use them only for reference.
`
`Conventions
`
`Caution: Information requiring particular attention
`Note:
`Footnote for items marked with Note in the text
`Remark: Supplementary information
`
`Related Documents
`
`Related documents indicated in this manual may include preliminary versions, but they may not be
`explicitly marked as preliminary.
`
`Document Name
`
`Document Number
`
`EDD1204ALTA, EDD1208ALTA, EDD1216ALTA DATA SHEET
`HOW TO USE SDRAM USER’S MANUAL
`
`E0136E
`E0123N
`
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`CONTENTS
`
`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM ...............................................................10
`1.1 Differences in Functions and Specifications .....................................................................................................11
`1.1.1 Data transfer frequency, data rate..............................................................................................................12
`1.1.2 Clock input .................................................................................................................................................13
`1.1.3 Data strobe signal (DQS) ...........................................................................................................................13
`1.1.4 Interface .....................................................................................................................................................14
`1.1.5 Power supply..............................................................................................................................................15
`1.1.6 /CAS read latency, /CAS write latency, burst length, and burst sequence .................................................15
`1.1.7 Use of DLL .................................................................................................................................................15
`1.1.8 Data mask..................................................................................................................................................15
`1.2 Differences in Commands ................................................................................................................................16
`1.2.1 Clock suspend............................................................................................................................................16
`1.2.2 Full-page burst ...........................................................................................................................................16
`1.2.3 Burst stop...................................................................................................................................................16
`1.2.4 Single write after burst read .......................................................................................................................16
`1.3 Differences in Operation Timing .......................................................................................................................17
`
`CHAPTER 2 PRODUCT OUTLINE..........................................................................................................................19
`2.1 Pin Configurations ............................................................................................................................................20
`2.2 Pin Functions....................................................................................................................................................22
`2.2.1 Clock input (CK, /CK).................................................................................................................................22
`2.2.2 Clock enable input (CKE)...........................................................................................................................22
`2.2.3 Chip select input (/CS) ...............................................................................................................................22
`2.2.4 Row address strobe input (/RAS), Column address strobe input (/CAS), Write enable input (/WE)...........22
`2.2.5 Address input (A0 to Ax) ............................................................................................................................23
`2.2.6 Bank Address input (BA0, BA1) .................................................................................................................23
`2.2.7 Data input/output (DQ0 to DQx).................................................................................................................24
`2.2.8 Data strobe input/output (DQS, LDQS, UDQS)..........................................................................................24
`2.2.9 DQ write mask enable input (DM, LDM, UDM)...........................................................................................24
`2.2.10 Power supply (for the internal circuit) (VDD, VSS) ......................................................................................24
`2.2.11 Power supply (for DQ) (VDDQ, VSSQ) .......................................................................................................24
`2.2.12 Referential voltage (VREF).........................................................................................................................24
`2.3 Block Diagram ..................................................................................................................................................25
`2.3.1 Memory cell array of 128M bit DDR SDRAM (EDD1216ALTA)..................................................................26
`2.3.2 Address decoder (Row address decoder, Column address decoder) ........................................................27
`2.3.3 I/O buffer....................................................................................................................................................27
`2.3.4 Refresh counter..........................................................................................................................................27
`2.3.5 DLL (Delay Locked Loop)...........................................................................................................................27
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`CHAPTER 3 PRODUCT FEATURES ......................................................................................................................28
`3.1 Synchronous Operation ....................................................................................................................................29
`3.2 Command Control.............................................................................................................................................30
`3.2.1 Command input timing ...............................................................................................................................30
`3.2.2 DDR SDRAM command table....................................................................................................................31
`3.3 MultiBank Operation .........................................................................................................................................32
`3.3.1 Four-bank configuration .............................................................................................................................32
`3.3.2 Multibank operations ..................................................................................................................................33
`3.4 Burst Operation ................................................................................................................................................34
`3.5 Access Time.....................................................................................................................................................36
`
`CHAPTER 4 INITIALIZATION...................................................................................................................................39
`4.1 Initialization after Power On..............................................................................................................................39
`
`CHAPTER 5 MODE REGISTER SET.....................................................................................................................41
`5.1 Programming the Mode Register......................................................................................................................41
`5.2 Parameters .......................................................................................................................................................41
`5.3 Mode Register and Extended Mode Register Fields (with 128M bit DDR SDRAM)..........................................46
`
`CHAPTER 6 SIMPLIFIED STATE DIAGRAM.........................................................................................................47
`6.1 Simplified State Diagram of DDR SDRAM........................................................................................................47
`6.2 Current State Definition ....................................................................................................................................49
`6.2.1 Idle (IDLE)..................................................................................................................................................49
`6.2.2 Bank activating (Row activating) ................................................................................................................49
`6.2.3 Bank active (BANK ACTIVE) (Row active).................................................................................................49
`6.2.4 Precharge ..................................................................................................................................................49
`6.2.5 Read and write (READ, WRIT)...................................................................................................................49
`6.2.6 Read and write with auto precharge (READA, WRITA)..............................................................................49
`6.2.7 Mode register set .......................................................................................................................................49
`6.2.8 CBR (Auto) refresh.....................................................................................................................................49
`6.2.9 Self refresh.................................................................................................................................................50
`6.2.10 Self refresh recovery ................................................................................................................................50
`6.2.11 Power down .............................................................................................................................................50
`
`CHAPTER 7 COMMAND OPERATIONS.................................................................................................................51
`7.1 DDR SDRAM Command Truth Table ...............................................................................................................51
`7.2 Command Execution Conditions.......................................................................................................................52
`7.3 Command Operation of 128M bit DDR SDRAM (EDD1216ALTA) ...................................................................53
`
`CHAPTER 8 BASIC OPERATION MODES ............................................................................................................59
`8.1 Read Mode .......................................................................................................................................................59
`8.2 Write Mode .......................................................................................................................................................62
`8.3 Refresh Mode ...................................................................................................................................................64
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`CHAPTER 9 DATA STROBE SIGNAL (DQS) CONTROL OPERATION.............................................................65
`9.1 Data Strobe Signal (DQS) ................................................................................................................................65
`9.1.1 Data strobe signal (DQS) in read cycle ......................................................................................................66
`9.1.2 Data strobe signal (DQS) in write cycle......................................................................................................67
`9.2 Relationship between Data Strobe Signal (DQS) / Output Data (DQ) and
`Clock (CK, /CK) during Read Cycle ..................................................................................................................68
`9.3 Relationship between Data Strobe Signal (DQS) and Output Data (DQ) in Read Cycle ..................................69
`9.4 Data Strobe Signal (DQS) Read Preamble and Read Postamble ....................................................................70
`9.5 Relationship between Data Strobe Signal (DQS) and Input Data (DQ) /
`DQ Write Mask Enable Signal (DM) during Write Cycle....................................................................................72
`9.6 Data Strobe Signal (DQS) Write Preamble and Write Postamble.....................................................................73
`
`CHAPTER 10 DQ WRITE MASK ENABLE SIGNAL (DM) CONTROL OPERATION ........................................74
`10.1 DQ Write Mask Enable Signal (DM) ...............................................................................................................74
`10.2 DQ Write Mask Enable Signal (DM) Control in Write Cycle............................................................................75
`10.3 DQ Write Mask Enable Signal (DM) Truth Table ............................................................................................75
`
`CHAPTER 11 CLOCK ENABLE SIGNAL (CKE) CONTROL OPERATION .........................................................76
`11.1 Basic Control ..................................................................................................................................................76
`11.2 Example of Clock Enable Signal (CKE) Control..............................................................................................77
`11.2.1 Power down mode....................................................................................................................................78
`11.2.2 Self refresh mode.....................................................................................................................................79
`11.2.3 Clock enable signal (CKE) command truth table (128M bit DDR SDRAM (EDD1216ALTA)) ..................80
`
`CHAPTER 12 BURST OPERATION........................................................................................................................82
`12.1 Terminating Burst Operation...........................................................................................................................82
`12.1.1 Data interrupt by read command..............................................................................................................82
`12.1.2 Data interrupt by write command .............................................................................................................84
`12.1.3 Ending burst operation by burst stop command .......................................................................................86
`12.1.4 Terminating burst operation by precharge command...............................................................................87
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`LIST OF FIGURES (1/2)
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`Figure No.
`
`Title
`
`Page
`
`Figure 1-1. 2-Bit Prefetch Architecture ........................................................................................................................12
`Figure 1-2. Clock Input................................................................................................................................................13
`Figure 1-3. SSTL_2 Interface (case of DIMM).............................................................................................................14
`Figure 1-4. DDR SDRAM Read Cycle Timing .............................................................................................................17
`Figure 1-5. SDR SDRAM Read Cycle Timing .............................................................................................................17
`Figure 1-6. DDR SDRAM Write Cycle Timing .............................................................................................................18
`Figure 1-7. SDR SDRAM Write Cycle Timing .............................................................................................................18
`
`Figure 2-1. Pin Configuration of 128M bit DDR SDRAM .............................................................................................20
`Figure 2-2. Pin Configuration of 256M/512M bit DDR SDRAM ...................................................................................21
`Figure 2-3. Block Diagram of 128M bit DDR SDRAM (EDD1216ALTA)......................................................................25
`Figure 2-4. Memory Cell Array of 128M bit DDR SDRAM (EDD1216ALTA) (Bank A) ................................................26
`
`Figure 3-1. DDR SDRAM Read Cycle Timing .............................................................................................................29
`Figure 3-2. DDR SDRAM Write Cycle Timing .............................................................................................................29
`Figure 3-3. Command Input Timing.............................................................................................................................30
`Figure 3-4. Four-Bank Configuration...........................................................................................................................32
`Figure 3-5. Burst Operation.........................................................................................................................................35
`Figure 3-6. Burst Read Cycle ......................................................................................................................................37
`Figure 3-7. Access Time of DDR SDRAM, SDR SDRAM and EDO DRAM ................................................................38
`
`Figure 4-1. Initializing DDR SDRAM ...........................................................................................................................40
`
`Figure 5-1. Mode Register/Extended Mode Register Set Cycle ..................................................................................41
`Figure 5-2. Read/Write Cycle with Burst Length of 8...................................................................................................42
`Figure 5-3. Burst Sequence ........................................................................................................................................43
`Figure 5-4. Timing Differences between /CAS Latency = 2 and 2.5............................................................................45
`Figure 5-5. Mode Register and Extended Mode Register fields (with 128M bit DDR SDRAM) ...................................46
`
`Figure 6-1. Simplified State Diagram of 128M bit DDR SDRAM (EDD1216ALTA) .....................................................48
`
`Figure 8-1. Read Cycle ...............................................................................................................................................60
`Figure 8-2. Read Cycle with Auto Precharge ..............................................................................................................61
`Figure 8-3. Write Cycle................................................................................................................................................62
`Figure 8-4. Write Cycle with Auto Precharge ..............................................................................................................63
`Figure 8-5. CBR (Auto) Refresh Cycle ........................................................................................................................64
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`LIST OF FIGURES (2/2)
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`Figure No.
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`Title
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`Figure 9-1. Relationship between Data Strobe Signal and Data Input/Output.............................................................65
`Figure 9-2. Data Strobe Signal in Read Cycle.............................................................................................................66
`Figure 9-3. Data Strobe Signal in Write Cycle.............................................................................................................67
`Figure 9-4. Data Strobe Signal and Output Data Timing as Related to Clock in Read Cycle......................................68
`Figure 9-5. Data Strobe Signal and Output Data in Read Cycle..................................................................................69
`Figure 9-6. Timing of Data Strobe Signal Read Preamble and Read Postamble 1 .....................................................71
`Figure 9-7. Timing of Data Strobe Signal Read Preamble and Read Postamble 2
`(Read-to-Read Data Bus transition) .........................................................................................................71
`Figure 9-8. Timing Parameters of DQ/DM during Write Cycle.....................................................................................72
`Figure 9-9. Timing of Data Strobe Signal Write Preamble and Write Postamble ........................................................73
`
`Figure 10-1. DQ Write Mask Enable Signal Control during Write Cycle ......................................................................75
`
`Figure 11-1. Signal Input Timing Controlled by Clock Enable Signal ..........................................................................76
`Figure 11-2. Example of Clock Enable Signal Control.................................................................................................77
`Figure 11-3. Power Down Mode..................................................................................................................................78
`Figure 11-4. Self Refresh Mode ..................................................................................................................................79
`
`Figure 12-1. Read/Read Command ............................................................................................................................82
`Figure 12-2. Write/Read Command ............................................................................................................................83
`Figure 12-3. Write/Write Command.............................................................................................................................84
`Figure 12-4. Read/Burst Stop/Write Command...........................................................................................................85
`Figure 12-5. Read/Burst Stop Command ....................................................................................................................86
`Figure 12-6. Read/Precharge Command ....................................................................................................................87
`Figure 12-7. Write/Precharge Command.....................................................................................................................88
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`LIST OF TABLES
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`Table No.
`
`Title
`
`Page
`
`Table 1-1. Differences in Functions and Specifications...............................................................................................11
`Table 1-2. SSTL_2 Interface Specifications ................................................................................................................15
`Table 1-3. Differences in Commands..........................................................................................................................16
`
`Table 2-1. Address Pins of 128M bit DDR SDRAM.....................................................................................................23
`Table 2-2. Bank Address and Selected Bank..............................................................................................................23
`
`Table 3-1. 128M bit DDR SDRAM (×4/×8/×16-bit Organization) Command List .........................................................31
`Table 3-2. Access Time of DDR SDRAM, SDR SDRAM and EDO DRAM .................................................................38
`
`Table 7-1. 128M bit DDR SDRAM (×4/×8/×16-bit Organization) Command Truth Table.............................................51
`Table 7-2. Command Executable Condition................................................................................................................52
`
`Table 9-1. AC Characteristics of Data Strobe Signal and Output Data in Read Cycle ................................................68
`Table 9-2. AC Characteristics of Data Strobe Signal and Output Data in Read Cycle ................................................69
`Table 9-3. AC Characteristics of Data Strobe Signal Read Preamble and Read Postamble ......................................70
`Table 9-4. AC Characteristics of DQ/DM in Write Cycle..............................................................................................72
`Table 9-5. AC Characteristics of Data Strobe Signal Write Preamble and Write Postamble.......................................73
`
`Table 10-1. DQ Write Mask Enable Signal Truth Table ..............................................................................................75
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
`
`DDR SDRAM (double data rate synchronous DRAM) is a type of DRAM that realizes twice the data transfer rate of
`conventional SDRAM (here after in this document, conventional SDRAM is referred to as SDR SDRAM (single data
`rate synchronous DRAM) in contrast with DDR SDRAM).
`
`This chapter explains the differences between DDR SDRAM and SDR SDRAM in the following areas.
`(1) Differences in functions and specifications
`(2) Differences in commands
`(3) Differences in operation timing
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
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`1.1 Differences in Functions and Specifications
`
`DDR SDRAM is a type of SDRAM that inherits technologies from SDR SDRAM and realizes faster operation and
`lower power consumption. It shares many common aspects with SDR SDRAM, which enables easy transition to DDR
`SDRAM.
`This section explains the differences in functions and specifications between DDR SDRAM and SDR SDRAM.
`
`Table 1-1. Differences in Functions and Specifications
`
`Item
`
`DDR SDRAM
`
`SDR SDRAM
`
`Data transfer frequency
`Data rate
`Clock input
`Data strobe signal (DQS)
`Interface
`Supply voltage
`/CAS read latency
`/CAS write latency
`Burst length
`Burst sequence
`Use of DLL
`Data mask
`
`Twice the operation frequency
`2/tCK
`Differential clock
`Essential
`SSTL_2
`2.5 V
`2, 2.5
`1
`2, 4, 8
`Sequential/Interleave
`Essential
`Write mask only
`
`Same as the operation frequency
`1/tCK
`Single clock
`Not supported
`LVTTL
`3.3 V
`2, 3
`0
`1, 2, 4, 8, full-page (256) Note
`Sequential/Interleave
`Option
`Write mask/Read mask
`
`Note Full-page (256) burst of SDR SDRAM is an option.
`
`Remark tCK: Clock cycle time
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
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`1.1.1 Data transfer frequency, data rate
`
`DDR SDRAM achieves a data transfer rate that is twice the clock frequency by employing 2-bit prefetch
`architecture.
`The 2-bit prefetch architecture is explained here using the read cycle as an example.
`In this architecture, 2n bits of data are transferred from the memory cell array to the I/O buffer every clock. Data
`transferred to the I/O buffer is output n bits at a time every half clock (both rising and falling edges of the clock (CK)).
`As the internal bus width is twice the external bus width, DDR SDRAM achieves a data output rate that is twice the
`data rate of the internal bus.
`Because data is accessed in 2-bit pairs, only burst lengths of 2, 4, and 8 are supported for DDR SDRAM.
`
`Figure 1-1. 2-Bit Prefetch Architecture
`
`/CK
`
`CK
`
`1 clock
`
`1/2 clock
`
`odd
`
`n bits
`
`DQx
`
`I/O Buffer
`
`Latch Circuit
`
`Memory
`Cell
`Array
`
`n bits
`n bits
`
`even
`
`n bits
`
`DQx
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
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`1.1.2 Clock input
`
`Due to the influence of various factors, the high-level period and low-level period of the clock input may not be the
`same (the duty ratio may not be 50%).
`In the case of SDR SDRAM, for which data input/output is only synchronized with the rising edges of the clock,
`there is some margin in the timing. However, in the case of DDR SDRAM, for which data input/output is synchronized
`with both the rising and falling edges of the clock, it is difficult to accurately control the data input/output timing based
`on the conventional single clock.
`Therefore, DDR SDRAM adopts a differential clock scheme that enables accurate memory control.
`
`Figure 1-2. Clock Input
`
`1 clock
`
`Single Clock
`(SDR SDRAM)
`
`Differential Clock
`(DDR SDRAM)
`
`CK
`
`/CK
`
`CK
`
`50%
`
`50%
`
`Dotted line shows the 50% duty ratio position.
`
`1 clock
`
`50%
`
`50%
`
`/CK is an input signal that has the same clock period but the reverse phase of CK. The high-level period and low-
`level period can be made equal by using the intersection of CK and /CK as an input reference level. In the case of
`DDR SDRAM, data input/output is synchronized with both the rising and falling edges of the data strobe signal (DQS),
`which has the same period as clock input CK.
`Employing a differential clock scheme enables DDR SDRAM to support a higher clock frequency and limit the
`negative influence of noise and other factors.
`
`1.1.3 Data strobe signal (DQS)
`
`Similarly to SDR SDRAM, DDR SDRAM is controlled by command input at the rising edge of the clock (CK), but
`the data input/output timing differs from that of SDR SDRAM. To achieve high-speed data transfer, DDR SDRAM
`adopts a data strobe signal (DQS). DQS is output from the device and received by the receiver, which adjusts the
`data (DQ) capture timing using DQS. For details, refer to CHAPTER 9 DATA STROBE SIGNAL (DQS) CONTROL
`OPERATION.
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`CHAPTER 1 DIFFERENCES BETWEEN SDRAM AND DDR SDRAM
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`1.1.4 Interface
`
`DDR SDRAM employs the JEDEC-compliant SSTL_2 (Stub Series Terminated Logic for 2.5V) interface to
`eliminate the signal degradation caused by noise and reflection produced as a result of a high operating frequency.
`SSTL-2 is a low-voltage (2.5V), small-amplitude and high-speed interface that reduces the effect of reflection by
`connecting series resistance between the signal branch point from the bus (stub) and the memory.
`
`(1) Stub resistance
`A stub resistance of approximately