UNITED STATES PATENT AND TRADEMARK OFFICE
`
`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`LENOVO (UNITED STATES) INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II LLC
`Patent Owner
`
`_________________
`
`Case No. IPR2024-01226
`Patent No. 7,646,835 B1
`___________________
`
`DECLARATION OF DUNCAN BAUSERMAN IN SUPPORT OF
`PETITION
`
`Petitioner Lenovo (United States) Inc. - Ex. 1022
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`1 of 7
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`_________________
`
`BEFORE THE PATENT TRIAL AND APPEAL BOARD
`
`_________________
`
`LENOVO (UNITED STATES) INC.
`Petitioner
`
`v.
`
`INTELLECTUAL VENTURES II LLC
`Patent Owner
`
`_________________
`
`Case No. IPR2024-01226
`Patent No. 7,646,835 B1
`___________________
`
`DECLARATION OF DUNCAN BAUSERMAN IN SUPPORT OF
`PETITION
`
`Petitioner Lenovo (United States) Inc. - Ex. 1022
`
`1 of 7
`
`
`
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`
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`I, Duncan Bauserman, make the following declaration pursuant to 28 U.S.C.
`
`§ 1746:
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`1.
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`2.
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`I am a patent agent at the law firm of Bookoff McAndrews PLLC.
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`I provide this Declaration in connection with the above-identified Inter
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`Partes Review proceeding requested at the United States Patent and Trademark
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`Office by Lenovo (United States) Inc. against Intellectual Ventures II LLC under
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`35 U.S.C. § 311, 37 C.F.R. § 42.104. Unless otherwise stated, the facts stated in
`
`this Declaration are based on my personal knowledge.
`
`3.
`
`Exhibit 1008 is a true and correct copy of Synchronous DRAM
`
`Architectures, Organizations, and Alternative Technologies by Bruce L. Jacob,
`
`published in December of 2002, which I personally downloaded online from the
`
`website https://user.eng.umd.edu/~blj/CS-590.26/references/DRAM-Systems.pdf
`
`on July 25, 2024. An exhibit label on the first page and page numbers on all pages
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`have been added to the bottom of this document but no other alterations have been
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`made.
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`4.
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`Exhibit 1009 is a true and correct copy of RAM Guide Part I: DRAM and
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`SDRAM Basics by Jon Stokes, published in July of 2000, which I personally
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`downloaded online from the website https://arstechnica.com/gadgets/2000/07/ram-
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`guide-part1-1/5/ on July 25, 2024. An exhibit label on the first page and page
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`2 of 7
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`numbers on all pages have been added to the bottom of this document but no other
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`alterations have been made.
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`5.
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`Exhibit 1010 is a true and correct copy of Design and PCB Layout
`
`Considerations for Dynamic Memories Interfaced to the Z80 CPU by Tim
`
`Olmstead, published in October of 1996, which I personally downloaded online
`
`from the website http://www.cpm.z80.de/download/dram.pdf on July 25, 2024. An
`
`exhibit label on the first page and page numbers on all pages have been added to
`
`the bottom of this document but no other alterations have been made.
`
`6.
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`Exhibit 1011 is a true and correct copy of A Performance Comparison of
`
`Contemporary DRAM Architectures by Vinodh Cuppu et al., published in May of
`
`1999), which I personally downloaded online from the website
`
`https://dl.acm.org/doi/pdf/10.1145/300979.300998 on July 25, 2024. An exhibit
`
`label on the first page and page numbers on all pages have been added to the
`
`bottom of this document but no other alterations have been made.
`
`7.
`
`Exhibit 1012 is a true and correct copy of How to Use DDR SDRAM by
`
`Elpida Memory, published in April of 2002, which I personally downloaded online
`
`from the website https://www.sjalander.com/research/thesis/pdf/ref6.pdf on July
`
`25, 2024. An exhibit label on the first page and page numbers on all pages have
`
`been added to the bottom of this document but no other alterations have been
`
`made.
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`3 of 7
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`8.
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`Exhibit 1013 is a true and correct copy of Hyundai Electronics Actively
`
`Supplying DDR SDRAM Modules to Major PC Makers by SK hynix, published in
`
`March of 2001, which I personally downloaded online from the website
`
`https://news.skhynix.com/hyundai-electronics-actively-supplying-ddr-sdram-
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`modules-to-major-pc-makers/ on July 25, 2024. An exhibit label on the first page
`
`and page numbers on all pages have been added to the bottom of this document but
`
`no other alterations have been made.
`
`9.
`
`Exhibit 1014 is a true and correct copy of SLDRAM: High Performance,
`
`Open-Standard Memory by Peter Gillingham et al., published in December of
`
`1997, which I personally downloaded online from the website https://www.ardent-
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`tool.com/CPU/docs/AMD/anatomy/misc/articles/gillingh.pdf on July 25, 2024. An
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`exhibit label on the first page and page numbers on all pages have been added to
`
`the bottom of this document but no other alterations have been made.
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`10. Exhibit 1015 is a true and correct copy of 3.1. How Memory Works with the
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`Processor by Technick, published in March of 1998, which I personally
`
`downloaded online from the website
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`https://technick.net/guides/hardware/umg/03_001/ on July 25, 2024. An exhibit
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`label on the first page and page numbers on all pages have been added to the
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`bottom of this document but no other alterations have been made.
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`4 of 7
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`11. Exhibit 1016 is a true and correct copy of Memory Access Scheduling by
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`Scott Rixner et al., published in March of 2000, which I personally downloaded
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`online from the website http://cva.stanford.edu/publications/2000/mas.pdf on July
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`31, 2024. An exhibit label on the first page and page numbers on all pages have
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`been added to the bottom of this document but no other alterations have been
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`made.
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`12. Exhibit 1017 is a true and correct copy of Computer-System Operation,
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`published in July of 1999 (last visited July 25, 2024), which I personally
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`downloaded online from the website https://www.slawinski.ca/courses/CS-
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`30/unit2/part1.htm on July 25, 2024. An exhibit label on the first page and page
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`numbers on all pages have been added to the bottom of this document but no other
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`alterations have been made.
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`13. Exhibit 1018 is a true and correct copy of Course-to-fine Estimation of
`
`Visual Motion by Eero P. Simoncelli, published in September of 1993, which I
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`personally downloaded online from the website
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`https://www.cns.nyu.edu/pub/eero/simoncelli93d.pdf on July 25, 2024. An exhibit
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`label on the first page and page numbers on all pages have been added to the
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`bottom of this document but no other alterations have been made.
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`14. Exhibit 1019 is a true and correct copy of excerpts from Modern Dictionary
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`of Electronics Seventh Edition by Rudolf F. Graf, published in February of 1999,
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`5 of 7
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`
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`depicting the definition of “automatic” and “buffer”, which I personally
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`downloaded online from the website
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`https://ia600200.us.archive.org/11/items/fe_Modern_Dictionary_of_Electronics_7t
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`h_Edithion/Modern_Dictionary_of_Electronics_7th_Edithion.pdf on July 25,
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`2024. An exhibit label on the first page and page numbers on all pages have been
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`added to the bottom of this document, and unnecessary pages have been deleted,
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`but no other alterations have been made.
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`15. Exhibit 1020 is a true and correct copy of excerpts from Merriam-Webster’s
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`Collegiate Dictionary Tenth Edition, published in 2000, depicting the definition of
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`“calibrate” and “systematic”, which I personally downloaded online from the
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`website https://archive.org/details/merriam-websters-collegiate-dictionary-10th-
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`edition/ on July 25, 2024. An exhibit label on the first page and page numbers on
`
`all pages have been added to the bottom of this document, and unnecessary pages
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`have been deleted, but no other alterations have been made.
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`16. Exhibit 1021 is a true and correct copy of Double Data Rate (DDR) SDRAM
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`Specification by JEDEC Solid State Technology Association, published in June of
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`2000, which I personally downloaded online from the website
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`https://img.114ic.com/tech/JESD79R1.pdf on July 25, 2024. An exhibit label on
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`the first page and page numbers on all pages have been added to the bottom of this
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`document but no other alterations have been made.
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`6 of 7
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`17.
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`In signing this declaration, I understand that willful and false statements and
`
`the like are punishable by fine or imprisonment, or both.
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`18.
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`I declare that all statements made herein of my knowledge are true, and that
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`all statements made on information and belief are believed to be true, and that
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`these statements were made with the knowledge that willful false statements and
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`the like so made are punishable by fine or imprisonment, or both, under Section
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`1001 of Title 18 of the United States Code.
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` I
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` declare under penalty of perjury that the foregoing is true and correct. Executed
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`this August 1, 2024, in Olathe, Kansas.
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`By: __________________
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`Duncan Bauserman
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`7 of 7
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