United States Patent 19
`Dewa et al.
`
`54) COMPUTER SYSTEM HAVING BIOS (BASIC
`INPUT/OUTPUT SYSTEM)-ROM (READ
`ONLY MEMORY) WRITING FUNCTION
`75 Inventors: Koichi Dewa; Kyoji Hayashi; Shigeru
`Satake, all of Tokyo, Japan
`73 Assignee: Kabushiki Kaisha Toshiba, Tokyo,
`Japan
`
`Appl. No.: 234,475
`21
`22 Filed:
`Apr. 28, 1994
`30
`Foreign Application Priority Data
`May 13, 1993
`JP
`Japan .................................... 5-111738
`Aug. 30, 1993
`JP
`Japan .................................... 5-213887
`(51) Int. Cl. .............................................. G06F 9/44
`52 U.S. Cl. ..................................... 395/700; 364/DIG. 1;
`364/28O.2
`58 Field of Search ....... 395/700; 364/DIG. 1 MS File
`
`56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,187,792 2/1993 Dayan et al. ........................... 3957725
`5,257,380 10/1993 Lang ................
`... 395/700
`5,261,04 1/1993 Bertram et al. ..
`... 395/700
`5,269,022 12/1993 Shinjo et al. ........
`... 364/DEG.
`5,327,531
`7/1994 Bealkowski et al. .............. 364/DIG. 1
`
`III IIHIIII
`US005522076A
`(11) Patent Number:
`5,522,076
`45 Date of Patent:
`May 28, 1996
`
`5,388,267 2/1995 Chan et al. ............................. 398/700
`FOREIGN PATENT DOCUMENTS
`4214184 11/1992 Germany .
`OTHER PUBLICATIONS
`Flash Memory Bios for PC and Notebook Computers, Jerry
`Jex, Intel Corporation, IEEE Pacific Rim Conference on
`Communications, Computers and Signal Processing, May
`9-10, 1991, pp. 692-695.
`Primary Examiner Thomas M. Heckler
`Attorney, Agent, or Firm-Limbach & Limbach; Alan S.
`Hodes
`ABSTRACT
`57)
`A flash memory used as a BIOS-ROM has a main block
`storing a BIOS and a boot block storing minimum programs
`executed in initializing the system. Upon a power-on opera
`tion, when a rewriting unit is connected to an expansion bus
`connector, a new boot block stored in a ROM of the
`rewriting unit is written in the flash memory. Upon the
`power-on operation, a key depression detecting routine in
`the boot block is executed to check whether a predetermined
`key is depressed. If the predetermined key is determined to
`be depressed, a rewriting program in a floppy disk is loaded
`in the system and executed, thereby rewriting the content of
`the main block into the BIOS file stored in the floppy disk.
`
`16 Claims, 13 Drawing Sheets
`
`POWER-0
`
`RESET
`
`B
`
`OUTPU ADDRESSFFFFF0 AND READ INSTRUCTION
`
`B3
`
`EXECUTE FAR JUMP NSTRUCON
`
`EXECUTE CRC AND KEY NPUT CHECK ROUNES
`
`Bt
`
`B
`
`NO
`SET FF 7 AND 73
`O HG EVEL
`
`BOO PROCESSNG
`
`B3
`
`B9
`
`B29
`
`
`
`SET FF 75 TO HG EVEL
`
`TRANSFER BOS FILE 8 FROM
`FDD 25 TO BIOS-ROM 7
`
`OSPLAY PROMP FOR
`POWERING SYSTEM OFF
`
`3
`
`B7
`NTIAZAON
`
`DISPLAY PROMP FOR
`NSERTNGFLOPY DISK
`B2 S KEY
`SQPERATIO
`
`
`
`B2 3
`
`825
`
`SPECIFC
`FES ESSE
`1,
`YES
`
`TRANSFERWRING ROUNE
`82 FROM FDD25 TOSYSTEM
`MEMORY 3
`
`83
`
`B2
`
`ID OATA
`EQUAL TO EACH
`OTHER
`2
`YES
`835
`
`NO
`
`DSPLAY
`ALAR
`MESSAGE
`
`Instacart, Ex. 1043
`
`1
`
`

`

`39
`
`--
`s's-390
`Ps
`
`U.S. Patent
`
`May 28, 1996
`
`Sheet 1 of 13
`
`5,522,076
`
`5
`BOS -
`O-ROM
`
`7
`
`3
`
`SYSTEM
`BU
`
`CO S.
`23
`
`FDC, WFO
`
`PSE-14
`P. cru
`SYSTEM
`O
`-------
`ODMAx2,PICx2.PT 2, SIOx2, PTCx
`HDD
`ONERAL-25
`OPRTI FDD
`4
`27
`
`C
`DISP - CONT
`O KBC - KB
`ERASS
`33
`3
`37
`F G.
`
`3.
`
`29
`BASEAY
`PANEL
`
`7
`BIOS-ROM / FFFF
`O TO
`DFFF
`
`
`
`SYSTEM
`AEENT
`
`
`
`CRC ROUTINE
`
`OOOO
`64 K------- OFFFF
`
`N
`
`ROUT NE
`
`
`
`2
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 2 of 13
`
`5,522,076
`
`FFFFFF
`
`FEO OOO
`FOFFFF
`
`A6M
`/ 28KBYTES
`/
`/ /
`/ /
`/ /
`/ /
`/ A
`7
`FOOOOO
`BIOS-ROM / is
`X 2N.J."
`/N N
`s OOOOO
`Y
`N M N
`OFFFFF
`K
`N 28KBYTES OEOOOO
`ODFFFF
`
`F G. 3 o
`
`OOOOOO
`
`FOOO: FFFF 28 K.
`A 20K
`
`7
`
`BIOS-ROMS
`BOOT BLOCK
`
`FOOO: FFFF 64K
`72
`
`
`
`7
`
`\BIOS-ROM
`
`
`
`
`
`SYSTEM
`MANAGEMENT
`ROUT NE
`
`FOOOOOOO 64K
`EOOO: FFFF
`T:
`MAN BLOCK
`
`OK
`FOOO : OOOO
`EO00 : FFFF 28 K
`20K
`
`BOO BLOCK
`
`SYSTEM
`MANAGEMENT
`ROUT NE
`
`F G. 4A
`
`EOOO: OOOO
`
`64K
`F G. 4B
`
`3
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 3 of 13
`
`5,522,076
`
`FF73
`
`NW
`
`47
`
`CPU
`
`FF7
`
`FE75
`
`MEMWTt
`MEMRDt
`
`
`
`ROMPRG
`+2V-N-O
`
`49
`--4--
`54
`
`A23
`
`A r SHE D
`
`st EEA y) D
`
`CPU
`
`PU
`
`-
`
`--
`
`A49
`
`A 8 A7
`
`53
`
`m
`
`57
`
`D
`
`A 6
`FFT DISE it
`
`D-sels,
`6
`
`D
`
`4
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 4 of 13
`7
`
`5,522,076
`
`10 WRITE->CK
`
`DSE it
`MASK CIRCUIT 49
`
`cru
`
`
`
`IIODATA
`I O WRITE
`
`V
`EXOR47
`
`ODATA
`10 WRITE
`
`RORS 45
`
`F G.
`
`7
`
`
`
`POWER - ON
`RESET
`EROM PSC39
`
`POWER - ON
`
`OPERATE ACCORDING TO PROGRAM OF BOOT
`BLOCK72, DO NOT CONVERT ADDRESS OF
`BQSRAM7, AND EXECUTE FAR JUMP
`INSTRUCTION," CRC, KEY INPUT CHECK ROUTINES
`
`A.
`
`
`
`
`
`
`
`NO ERROR <ced ERROR
`
`2 KEY PEPRESSED
`
`
`
`A3
`
`
`
`
`
`CONVERT ADDRESS OF BIOS-ROM
`7 MASK ADDRESSES
`E000 : 0000 TO E000 : FFFF
`QEBIOSROM7, AND
`BOOTSTRAPOS
`
`
`
`
`
`TRANSFER BOS REWRTNG
`PROGRAM N REWRTNG FO 80
`FOR BIOS-ROM TO SYSTEM
`MEMORY BY LOAD ROUT NE TO
`REWRTE BIOS-ROM
`F G. 8
`
`
`
`
`
`5
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 5 of 13
`
`5,522,076
`
`POWER-ON
`
`RESET
`
`B
`
`OUTPUT ADDRESS FFFFFO AND READ NSTRUCTION
`
`B3
`
`EXECUTE FAR JUMP NSTRUCTION
`
`EXECUTE CRC AND KEY NPUT CHECK ROUTINES
`
`YES
`
`NO
`
`B5
`
`B7
`
`F 2 KE
`(EPRgSS ED
`NO
`SET FF 7 AND 73
`TO HGH EVEL
`
`B3
`
`B7
`NTAL, ZATION
`
`BOOT PROCESSNG
`
`B5
`
`B49
`
`DSPLAY PROMPT FOR
`NSERTNG FLOPPY DISK
`
`* -1S KEY
`QPERATION
`
`
`
`B23
`
`B29
`
`
`
`SET FF 75 TO HGH LEVEL
`
`
`
`TRANSFER BIOS FE 8 FROM
`FDD 25 TO BIOS-ROM 7
`
`
`
`Fissen
`IFD
`B25
`YES
`SSESSINES
`
`MEMORY 3
`
`DISPLAY PROMPT FOR
`POWERING SYSTEM OFF
`
`B3
`
`
`
`B3
`
`F G. 9
`
`B27
`ID DATA
`EQUAL TO EACH
`OTES
`YES
`B35
`
`NO
`
`DISPLAY
`ALARM
`MESSAGE
`
`6
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 6 of 13
`
`5,522,076
`
`FD
`
`8O
`
`WRTNG
`ROUTINE
`
`
`
`
`
`82
`
`BOS FLE
`
`8
`
`F G. O
`
`OOOOOH
`
`90 Mx 8BIT
`
`PRINTER FRMWARE
`256 KB
`MENU/ PIM aoke
`
`
`
`PRINTER FIRMWARE ROM 123
`MENU ROM 27
`
`BOOT BLOCK
`
`
`
`DFFFFH
`EOOOOH
`
`EFFFFH
`
`/
`/
`-
`SYSTEM BIOS 64KB STEM
`28" /
`?
`FOOOOH supreventary
`FFFFO
`A (i.
`FBFFFH
`ADDRESS
`FCOOOH
`BOOT BLOCK 8KB
`FFFFFH Hu- - - - - - - - - - -
`
`SUPPLEMENTARY
`
`W
`
`7
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 7 of 13
`
`5,522,076
`
`A
`
`35
`y
`
`ON-BOARD
`- PRNTER
`CONTROLLER
`
`I O
`GA
`
`CPU 46MHz
`80386SX
`MAN
`MEMORY
`option
`EXPANSION
`EMSRY---4-3
`2M14M18MB
`DMA
`CONTROLLER
`NTERRUPT
`CONTROLLER
`
`2
`
`CS
`
`4.
`
`5
`
`440
`
`29
`
`
`
`FDD
`CONTROLLER
`
`
`
`ON-BOARD
`PRINTER
`36
`
`37,
`ETAL -
`forms
`40M 160MB -
`T K f Fe s 4. 4. M
`
`38
`
`39
`
`MER
`
`6
`
`PRINTER
`CONTROLLERN-30
`
`FDDI PRT
`CONNECTOR
`
`REAL-TIME h-7
`CLOCK
`
`48
`
`9
`
`20
`
`2
`22
`
`23
`
`BACK-UP
`RAM32KB
`KANJR
`(64ke spacity
`DCT ONARY
`ROM 52KB
`64KB 8PAGE)
`
`m EM
`(64KB 8PAGE)
`
`AESION
`64.
`PAGE)
`PRNTER
`| FIRMWARE
`ROM 256KB
`L-64KBAP -
`USERT
`ROM
`24
`43
`
`F G
`
`RS-232C
`CONTROLLER
`
`3.
`
`RS-232C
`PS 2MOUSE
`
`40
`
`85-KEY
`856EER 32
`KEYBOARD
`ESR6 ER
`. . d is
`33 4
`X
`D MONOCHROME
`VRAM
`DC-0UT (5-12.7:22)
`32 KB
`AC-N
`
`
`
`POWER SUPPLY
`
`
`
`42
`
`OUT NE
`FONT ROM R-25
`BMB
`(64 KB 428 PAGE)
`
`27
`
`44
`BOOT BLOCK
`REW RTNG
`UNT
`
`ENE -126
`- aves) is tro"
`RW 640KB
`(64KB OPAGE)
`SYSTEM
`28
`ROM 128KB -
`------- (64KBx 2PAGE)--
`ENSION
`CONNECTOR
`
`8
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 8 of 13
`
`5,522,076
`
`MEMORY AREA
`MANAGED BY CPU
`OOOOOOH SYSTEM MORY
`MEMORY 640KB
`
`OAOOOOH
`OB8OOOH
`OCOOOOH
`OOOOOOH
`
`OEOOOOH
`
`OE8OOOH
`
`
`
`VRAM. 32KB
`
`
`
`EMS WINDOW
`64KB
`H-RAM WINDOW
`32KB
`BACKUP RAM
`
`
`
`O
`-
`i
`H
`
`OEFFFFH
`of0000 SYSTEMB12S
`
`systEMBios
`
`SUPPLET
`MENTARY
`,
`ROM 64KB
`BOOT BLOCK
`- - - - - - - - - - - - - - -
`
`OOOOOH
`
`
`
`2OOOOOH
`
`4OOOOOH
`
`6OOOOOH
`
`AOOOOOH
`FFOOOOH
`
`FFFFFFH
`
`2 MB
`STANDARD
`MEMORY
`
`EXPANSON
`MEMORY 2MB
`
`
`
`SYSTEM BIOS
`ROM 64KB
`
`F G.
`
`3
`
`9
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 9 of 13
`
`5,522,076
`
`
`
`
`
`
`
`
`
`
`
`OF:FFFFh
`
`BOO BLOCK
`(PARAMETER
`
`SYSTEM
`BOS
`64KB
`
`
`
`
`
`
`
`ADDRESS
`CONVERSION
`A. RERS ON)
`
`F G.
`
`4
`
`SUPPLEMEN
`TARY
`
`BOO BLOCK
`(PARAMETER)
`
`10
`
`

`

`U.S. Patent
`
`
`
`May 28, 1996
`
`Sheet 10 of 13
`
`5,522,076
`
`
`
`
`
`l'ESB}} ISWW XT10
`
`
`
`
`
`W 0}}
`
`30EMA
`
`
`
`WOHdGE HSVT-I
`
`G? 9 | -!
`
`11
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 11 of 13
`
`5,522,076
`NEW BOOT BLOCK
`
`
`
`W
`
`BOS
`ENER
`NTALZNG
`ROUTINE
`ADDRESS
`D
`CONVERTNG
`ROUTINE
`CRC ROUTINE
`
`2O
`
`ROM
`ADDRESS
`YEING
`BOOT BLOCK
`WINDOW OPEN
`ROUTINE
`BOOT BLOCK
`TRANSFER
`ROUTINE
`BOOT BLOCK
`
`OOOOH
`
`
`
`
`
`
`
`
`
`
`
`FF FOH
`(START ADDRESS)
`FFFFH
`
`
`
`
`
`
`
`
`
`C
`
`C3
`
`
`
`
`
`
`
`
`
`
`
`
`
`DISPLAY PROMPT FOR
`POWERNG SYSTEM OFF
`
`F G. 18
`
`C
`
`C43
`
`12
`
`

`

`May28, 1996
`
`Sheet 12 of 13
`
`iv2
`
`
` |Orv!Y1SI93H“OHLNOD:ASOWAW
`HSV'14|
`
`U.S. Patent
`
`|||Ley
`
`
`
`0-¢2vViVG0/1
`
`
` (MOGNIM|YLUSANIOTeND||£2OHVNOLLWNINNAlsa!ONVYSSauGaY||
`
`
`jl|||
`
`|||80S|
`
`copt-zorvor
`
`5,522
`
`076
`
`9
`
`OHWYO-ezV13S3YASW90Yd
`
`peorpeorvorSok]
`
`Yd
`
`HOOO004
`
`LINDYID
`
`13
`
`13
`
`
`
`
`
`
`

`

`U.S. Patent
`
`May 28, 1996
`
`Sheet 13 of 13
`
`5,522,076
`
`
`
`-
`
`SEC
`
`LATCH
`
`-
`FIG20As —/ N
`F. G.2OBRESET — —
`F. G.20CMAST —
`
`14
`
`

`

`1.
`COMPUTER SYSTEM HAVING BIOS (BASIC
`INPUT/OUTPUT SYSTEM)-ROM (READ
`ONLY MEMORY) WRITING FUNCTION
`
`BACKGROUND OF THE INVENTION
`
`1. Field of the Invention
`The present invention relates to a computer system using
`a programmable ROM such as a flash EEPROM (Electri
`cally Erasable and Programmable Read Only Memory) as a
`BIOS-ROM and, more particularly, to a computer system
`having a rewriting function using a rewriting floppy disk or
`a computer system capable of executing rewriting upon
`connecting a dedicated unit to a bus.
`2. Description of the Related Art
`A computer System such as a personal computer generally
`has a system ROM (Read Only Memory) for storing a BIOS
`(Basic Input/Output System). When the contents of this
`system ROM are destroyed or to be upgraded, this system
`ROM must be replaced with a new or corresponding one.
`In recent years, a flash EEPROM (Electrically Erasable
`and Programmable Read Only Memory) is developed as a
`programmable ROM. This flash EEPROM has various
`advantages including one that storage data can be erased in
`units of blocks. For this reason, a configuration using this
`flash EEPROM as a system ROM to rewrite the BIOS has
`recently been employed.
`In a system using such a flash EEPROM, to rewrite the
`BIOS, a BIOS rewriting utility is loaded from a floppy disk
`to the main memory upon bootstrap of the operating system.
`This system is disclosed in a U.S. Ser. No. 07/958,556 filed
`Oct. 8, 1992 by the same applicant.
`When the flash EEPROM is used as a system ROM as
`described above, the BIOS can be rewritten on-board even
`after the shipment of a computer product. More specifically,
`to rewrite the BIOS held in the system ROM, the user need
`not open the housing of the computer unit which incorpo
`rates the BIOS-ROM nor replace a chip holding the old
`BIOS with a new chip. Therefore, when a flash EEPROM as
`a rewritable ROM is applied to the BIOS-ROM, BIOS
`revision can be facilitated.
`A BIOS rewriting process is based on an assumption that
`a system. Such as a personal computer is normally initialized
`and set in a BIOS rewriting process utility execution state.
`The computer initialization processing, i.e., OS (Operating
`System) bootstrapping can be performed by executing a boot
`routine in the BIOS.
`When the contents of the BIOS are destroyed, the oper
`ating system itself cannot be bootstrapped, and the BIOS
`rewriting utility cannot be executed. The BIOS contents may
`be destroyed by hardware faults or a power-OFF operation
`during the BIOS rewriting process.
`Particularly, in recent years, a user can download a BIOS
`compatible with his own computer system or an upgraded
`BIOS to his own floppy disk through personal computer
`communication. The user can freely rewrite the BIOS using
`this floppy disk. In this manner, under circumstances
`wherein the user can freely rewrite the BIOS without using
`any special device, the BIOS may be destroyed during the
`rewriting process due to some reason such as accidental
`power-OFF
`When the BIOS is destroyed, it cannot be rewritten, and
`the contents of the BIOS cannot be repaired. In this case, the
`user must replace the flash EEPROM storing the BIOS with
`a new one storing the normal BIOS.
`
`10
`
`15
`
`20
`
`25
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`5,522,076
`
`2
`A trouble may also occur when a failure occurs in a
`boot-block program, but not in the BIOS stored in the flash
`EEPROM due to the following reason. The boot block of the
`flash EEPROM should be executed first in initializing the
`system. When the contents of the boot block are destroyed,
`various processes such as BIOS content check cannot be
`performed. In addition, the system cannot be bootstrapped.
`Therefore, when the contents stored in the flash EEPROM
`used as the BIOS-ROM are destroyed, the flash EEPROM
`itself must be replaced.
`
`SUMMARY OF THE INVENTION
`It is an object of the present invention to provide a
`computer system for repairing a program on-board without
`replacing a flash EEPROM used as a BIOS-ROM with a new
`one even under the circumstances wherein the contents of a
`BIOS or boot-block area are destroyed to disable bootstrap
`ping of the system.
`In order to achieve the above object, according to the first
`aspect of the present invention, there is provided a computer
`system comprising: a programmable internal memory for
`Storing a program group executed to bootstrap the system,
`external memory means having a repairing program for
`repairing the program group; and control means for execut
`ing the repairing program in the external memory means to
`control and repair the program group in the internal memory
`upon a power-on operation when a failure occurs in the
`program group to disable normal bootstrapping of the sys
`te.
`In the above arrangement, when some failure occurs in the
`internal memory, e.g., the EEPROM used as a system ROM
`to prevent bootstrapping of the computer system, the pro
`gram in the external memory is executed first when the
`computer system is powered on. The program for repairing
`various programs in the internal memory is stored in this
`external memory. Upon executing this repairing program,
`the programs in the internal memory are repaired. In this
`manner, even if a failure occurs in the internal memory to
`interfere bootstrapping of the computer system, the internal
`memory need not be replaced, and the various programs can
`be repaired on-board because the programs in the internal
`memory can be repaired.
`It is the second object of the present invention to provide
`a computer system capable of forcibly executing a BIOS
`rewriting utility to rewrite the BIOS on-board even if the
`BIOS is destroyed and the system cannot be bootstrapped.
`It is the third object of the present invention to provide a
`computer system having a function of receiving a command
`from a user in bootstrapping the system and rewriting a
`BIOS in accordance with the command from the user.
`In order to achieve the second and third objects, according
`to the second aspect of the present invention, there is
`provided a computer system comprising: a keyboard, having
`a plurality of keys, for receiving various instructions; a main
`memory arranged in a computer system main body; a first
`memory having a first memory area for storing a boot
`program for bootstrapping the computer system and various
`basic input/output programs for controlling hardware, and a
`Second memory area for storing a key depression detecting
`program for detecting depression of a predetermined key of
`the keyboard and a load program for loading a program for
`rewriting the first memory area; a second memory storing a
`rewriting program for rewriting a content of the first
`memory area and capable of being inserted into the com
`puter system main body; key depression detecting means for
`
`15
`
`

`

`5,522,076
`
`O
`
`15
`
`20
`
`25
`
`30
`
`35
`
`3
`executing the key depression detecting program in the
`second memory area upon a power-on operation of the
`computer system to detect depression of the predetermined
`key of the keyboard; boot means for executing the boot
`program in the first memory area when the key depression
`detecting means does not detect the depression of the
`predetermined key; load means for executing the load pro
`gram in the second memory area to load the rewriting
`program from the second memory to the main memory when
`the key depression detecting means detects the depression of
`the predetermined key; and rewriting means for executing
`the rewriting program loaded in the main memory to rewrite
`the content of the first memory area.
`In this arrangement, the EEPROM used as the system
`ROM has the first memory area as a target object rewritten
`by the rewriting program and the second memory area not
`subjected to the rewriting. The key depression detecting
`program stored in the second memory area is executed upon
`a power-on operation. When the key depression detecting
`program is executed, the presence or absence of depression
`of the predetermined key for designating rewriting of the
`first memory area is determined. If the predetermined key is
`not depressed, the boot program in the first memory area is
`executed to bootstrap the operating system. However, when
`the depression of the predetermined key is detected, the load
`program stored in the second memory area is executed prior
`to execution of the boot program in the first memory area.
`When this load program is executed, the rewriting program
`is forcibly loaded from the external memory and executed.
`As a result, the contents of the second memory area are
`rewritten.
`As described above, the rewriting program can be forcibly
`executed upon depressing the predetermined key. For this
`reason, even if the contents of the programmable first
`memory area are destroyed to disable bootstrapping of the
`system, the contents of the first memory area can be repaired
`on-board.
`It is the fourth object of the present invention to provide
`a computer system, connected to a dedicated unit, capable of
`repairing a program on-board, even if a program to be
`executed first is destroyed.
`In order to achieve the fourth object, according to the third
`aspect of the present invention, there is provided a computer
`system comprising: a system bus for transmitting various
`data and an address, a memory including a boot area which
`is mapped to a first predetermined address range of a system
`address space and stores a program group executed in
`bootstrapping the computer system; a memory unit, having
`a memory area mapped to the same first address range as that
`of the boot area and detachable from the system bus, the
`memory area storing a rewriting program for repairing a
`content of the boot area, detecting means for detecting that
`the memory unit is connected to the system bus; means for
`disabling access to the memory when the detecting means
`detects that the memory unit is connected to the system bus;
`means for accessing the memory unit on the basis of an
`address for designating the boot area, executing the rewrit
`ing program, and repairing the content of the boot area; and
`remapping means for remapping the boot area of the
`memory to a second predetermined address range different
`from the first address range to enable access to the memory
`on the basis of the second address range.
`In this arrangement, when the memory unit is connected
`to the memory bus, access to the memory (EEPROM) is
`disabled. When a system address belonging to the first
`address range is issued, this address is sent to the memory
`
`45
`
`50
`
`55
`
`60
`
`65
`
`4
`unit through the system bus without any modification,
`thereby accessing the memory area of the memory unit. For
`this reason, the rewriting program stored in the memory unit
`is executed to start a process for rewriting the boot area. In
`this case, the boot area of the memory is remapped to the
`second address range so that the memory unit and the
`address range do not overlap each other. The boot area is
`write-accessed through the second address range. Therefore,
`even if the boot area which stores the program to be
`executed first in bootstrapping the system is destroyed, the
`contents of the boot area can be repaired without replacing
`the memory (flash EEPROM).
`Additional objects and advantages of the invention will be
`set forth in the description which follows, and in part will be
`obvious from the description, or may be learned by practice
`of the invention. The objects and advantages of the invention
`may be realized and obtained by means of the instrumen
`talities and combinations particularly pointed out in the
`appended claims.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The accompanying drawings, which are incorporated in
`and constitute a part of the specification, illustrate presently
`preferred embodiments of the invention and, together with
`the general description given above and the detailed descrip
`tion of the preferred embodiments given below, serve to
`explain the principles of the invention.
`FIG. 1 is block diagram showing the arrangement of a
`computer system according to the first embodiment of the
`present invention;
`FIG. 2 is a block diagram showing the contents of data
`stored in a BIOS-ROM shown in FIG. 1;
`FIG. 3 is a memory map for explaining an address space
`area allocated to the BIOS-ROM of the first embodiment;
`FIG. 4A is a view showing the relationship between the
`address space allocated to the BIOS-ROM and the area in
`the BIOS-ROM immediately after a power-on operation of
`the computer system;
`FIG. 4B is a view showing the relationship between the
`address space allocated to the BIOS-ROM and the area in
`the BIOS-ROM during an operation of the computer system;
`FIG. 5 is a block diagram showing a hardware arrange
`ment for controlling an address allocated to the BIOS-ROM
`of the first embodiment,
`FIG. 6 is a block diagram showing the arrangement of a
`mask circuit shown in FIG. 5;
`FIG. 7 is a block diagram showing a hardware arrange
`ment for generating a control signal used in hardware shown
`in FIG. 5;
`FIG. 8 is a flow chart for generally explaining an opera
`tion for bootstrapping the computer system of the first
`embodiment,
`FIG. 9 is a flow chart for explaining the operation shown
`in FIG. 8 in detail;
`FIG. 10 is a memory map showing the structure of a
`floppy disk for storing a BIOS file to be transferred to the
`BIOS-ROM of the first embodiment;
`FIG. 11 is a block diagram showing the arrangement of a
`computer system according to the second embodiment of the
`present invention;
`FIG. 12 is a view showing storage the contents of a flash
`EEPROM arranged in the system of the second embodi
`ment,
`
`16
`
`

`

`5,522,076
`
`S
`FIG. 13 is a view showing a memory map in the system
`of the second embodiment;
`FIG. 14 is a view showing address allocation to the flash
`EEPROM in the system of the second embodiment;
`FIG. 15 is a block diagram showing the hardware arrange
`ment near the fiash EEPROM of the second embodiment and
`the arrangement of a boot-block rewriting unit arranged in
`this system;
`FIG. 16 is a view showing the storage contents of a ROM
`10
`arranged in the boot-block rewriting unit in FIG. 15;
`FIG. 17 is a diagram showing a circuit arrangement for
`controlling a flash EEPROM arranged in the system of the
`second embodiment,
`FIG. 18 is a flow chart for explaining an operation of the
`second embodiment;
`FIG. 19 is a diagram for explaining the arrangement of a
`master signal generator shown in FIG. 15; and
`FIGS. 20A to 20O are timing charts for explaining the
`generation timing of a master signal (MAST) and the latch
`timing of the master signal, in which FIG. 20A shows the
`timing of a power-on reset signal (PCLR), FIG. 20B shows
`the timing of a system reset signal (RESET), and FIG. 200
`shows the timing of the master signal.
`
`15
`
`20
`
`6
`The Super Integration IC (SI) 23 incorporates a floppy
`disk controller (FDC) for controlling a floppy disk drive and
`a variable frequency oscillator (VFO) for generating an FDC
`clock. This SI 23 can comprise a T9920 available from
`TOSHIBA CORP.
`The SI 23 is connected to a floppy disk drive (internal
`FDD) 25 as a standard floppy disk drive in the computer. An
`external floppy disk drive or printer (PRT/FDD) 27 is
`connected to the SI 23, as needed. In addition, a power
`supply controller (PSC) 39 for controlling a system power
`supply 41 is connected to the SI 23. The PSC39 has a switch
`39a and outputs a power-on reset signal when the system is
`powered on using this switch 39a.
`A display controller (DISP-CONT) 29 is connected to the
`system bus 15. This display controller 29 controls to display
`information on a display panel 31 of an LCD (Liquid Crystal
`Display) or the like.
`A keyboard controller (KBC) 33 is connected to the
`system bus 15. This keyboard controller 33 scans the key
`matrix of a keyboard (KB) connected to the keyboard
`controller 33, receives a signal corresponding to a depressed
`key, and converts this signal into a predetermined key code.
`This key code is transmitted to the CPU 11 through the
`system bus 15 in accordance with handshake serial commu
`nication.
`An expansion connector 37 is connected to the system bus
`15. An expansion unit (expansion board) for expanding the
`functions can be connected to this expansion connector 37.
`The arrangement of the BIOS-ROM 17 and a memory
`space (address space) allocated to this BIOS-ROM 17 will
`be described with reference to FIGS. 2 to 4B.
`The BIOS-ROM 17 comprises a flash memory having a
`memory capacity of 8 bitsX128 k, i.e., 128 kbytes. As shown
`in FIG. 2, the first 120-kbyte area of the BIOS-ROM 17, i.e.,
`an area from physical addresses 00000H to 1DFFFH serves
`as a main block 17a to be written by a BIOS rewriting
`program (to be described later). Note that a suffix "H'
`represents hexadecimal notation. In the following expres
`sions concerning addresses, “H” is omitted.
`An 8-kbyte area following the first 120-kbyte area, i.e., an
`area from physical addresses 1E000 to 1FFFF serves as a
`read-only boot block 17b not to be rewritten. Write access to
`the boot block 17b is inhibited by a hardware logic arranged
`in the SI 19 or 29. The entire area of the flash memory
`constituting the BIOS-ROM 17 is programmable if the flash
`memory is removed from the system board and a flash
`memory writer is used. However, in an on-board state, only
`the main block 17a is rewritable. Write access to the boot
`block 17b is inhibited by a hardware logic for inhibiting
`generation of a program signal. Note that the BIOS-ROM 17
`can comprise, e.g., an i28F001BX-T available from Intel.
`The boot block 17b in the BIOS-ROM 17 is an area in
`which programs for performing minimum functions for
`system control are stored. The boot block 17b stores a Far
`Jump Instruction 17c, a CRC (Cyclic Redundancy Check)
`routine 17d for performing error detection of data stored in
`the BIOS-ROM 17, and a routine (address converting and
`masking routine) 17e for performing address conversion and
`masking of the BIOS-ROM 17.
`This boot block 17b also stores an initialization routine
`17f for executing minimum initialization processing, a load
`routine 11g for transferring a writing routine for rewriting
`the BIOS-ROM 17 from the floppy disk drive (FDD) 25 to
`the system memory 13, a key depression detecting routine
`17h for detecting the depression/nondepression of a prede
`termined key for designating rewriting of the main block
`17a, and ID (identifier) data 17i used to determine whether
`
`25
`
`DETALED DESCRIPTION OF THE PREFERRED
`EMBODIMENTS
`(First Embodiment)
`The first embodiment of the present invention will be
`described with reference to the accompanying drawings.
`FIG. 1 shows the arrangement of a personal computer
`system according to an embodiment of the present inven
`tion. This personal computer is a portable computer and
`comprises a CPU (Central Processing Unit) for controlling
`the overall computer system. A CPU 11 can comprise a chip
`having an arrangement and functions equivalent to an
`80486SL available from Intel. Corp.
`A system memory 13 is connected to the CPU 11 through
`a local bus. This system memory 13 is used as the main
`memory of this personal computer system. The system
`memory 13 holds programs and data which serve as pro
`cessing targets. In this embodiment, the system memory 13
`has a standard memory capacity of 2 Mbytes. The system
`memory 13 can be expanded to a maximum of 18 Mbytes by
`connecting an expansion memory to an expansion slot 14.
`The CPU 11 is connected to a system bus 15. This system
`bus 15 is used to transfer address data, data, and control data.
`A BIOS-ROM 17 for storing a BIOS (Basic Input/Output
`System) and the like is connected to the system bus 15. This
`BIOS-ROM 17 is constituted by a flash EEPROM (to be
`referred to as a flash memory hereinafter). The details of the
`BIOS-ROM 17 will be described with reference to FIGS. 2
`to 4B.
`A Super Integration IC (SI) 19 is also connected to the
`system bus 15. This SI 19 incorporates two DMA (Direct
`Memory Access) controllers for controlling direct memory
`access, two programmable interrupt controllers (PICs), two
`programmable interrupt timers (PITs), two serial input/
`output interfaces (SIOs), and one real-time clock (RTC).
`This SI 19 can comprise an 2360SL available from Intel.
`A hard disk drive (HDD) 21 and a Super Integration IC
`(SI) 23 are connected to the system bus 15. The hard disk
`drive (HDD) 21 has an IDE (Integrated Device Electronics)
`interface and is directly access-controlled by the CPU 11.
`This 2.5" hard disk drive (HDD) 21 has a memory capacity
`of 120 Mbytes/200 Mbytes.
`
`30
`
`35
`
`40
`
`45
`
`50
`
`55
`
`60
`
`65
`
`17
`
`

`

`7
`a BIOS to be written is compatible with the target computer
`system model in rewriting the BIOS. This ID data 17i is
`stored in an area starting from address 1E000. The Far Jump
`Instruction 17c is stored in an area starting from address
`1FFFO of the BIOS-ROM 17. This area is an area first
`addressed by the CPU 11 when the system is powered on,
`thereby executing various programs in the boot block 17b.
`On the other hand, a BIOS including an IRT (Initial
`Reliability Test) and the like, e.g., a BIOS compatible with
`a conventional personal computer, is stored in the first
`64-kbyte area (low memory area) of the main block 17a in
`the BIOS-ROM 17. Aboot routine for loading the IPL of the
`operating system in the system memory 13 and bootstrap
`ping the operating system is stored in this area. A system
`management routine is stored in the remaining 56-kbyte area
`(high memory area) following the first 64-kbyte area of the
`main block 17a. This system management routine is a
`program for executing processes such as setup, power-save,
`suspend, and resume processes.
`Two spaces are allocated to the 128-kbyte area of the
`BIOS-ROM 17 as address spaces accessed by the CPU 11,
`as shown in FIG. 3. In the 16-Mbyte address space, a
`High-side 128-kbyte area (addresses FE000 to FFFFF) of
`the 1-Mbyte between the 15th Mbyte and the 16th Mbyte,
`and a High-side 128-kbyte area (addresses OE000 to OFFFF)
`of the first 1-Mbyte appear to be present. Access cannot
`always be performed using addresses corresponding to these
`areas. Data are present in different spaces depending on
`whether the system is initialized or in the subsequent normal
`operating state. This is to cope with the real or protect mode
`30
`of the CPU 11.
`The addresses of the BIOS-ROM 17 in the address space
`viewed from the CPU 11 are allocated as follows upon
`power-on of the system. As shown in FIG. 4A, the Low-side
`(first half) 64-kbyte area is allocated to E000 (segment
`address): 0000 (intrasegment address) to E000: FFFF, and
`the High-side (second half) 64-kbyte area is allocated to
`F000:0000 to F000: FFFF. On the other hand, in the normal
`state, as shown in FIG. 4B, the Low-side 64-kbyte area of
`the BIOS-ROM 17 is allocated to F000:0000 to F000: FFFF,
`and the High-side 64-kbyte area is allocated to E000: 0000
`to E000: FFFF. That is, when viewed from the CPU 11, the
`addresses of the Low-side 64-kbyte area and the High-side
`64-kbyte area of the BIOS-ROM 17 are reversed between
`the system initialization and the normal operation, as can be
`45
`apparent from comparison between FIGS. 4A and 4B. The
`details of such address conversion will be described with
`reference to FIG. 5.
`A circuit arrangement mainly including an address circuit
`for addressing the BIOS-ROM 17 is shown in FIG. 5.
`The BIOS-ROM 17 receives 17 address bits A0 to A16
`corresponding to the 128-kbyte memory capacity, a chip
`select signal