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`Case 2:20-cv-00048—JRG Document 1-2 Filed 02/21/20 Page 1 of 12 PageID #: 123
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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 2 of 12 PageID #: 124
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`USOO8288269B2
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`(12) United States Patent
`Hall et al.
`
`(10) Patent No.:
`(45) Date of Patent:
`
`US 8,288,269 B2
`Oct. 16, 2012
`
`(54) METHODS FORAVOIDING PARASITIC
`CAPACITANCE IN AN INTEGRATED
`CIRCUIT PACKAGE
`
`(75) Inventors: Jeffrey Hall, San Jose, CA (US); Shawn
`Nikoukary, Santa Clara, CA (US);
`Amar Amin, Milpitas, CA (US);
`Michael Jenkins, San Jose, CA (US)
`Assignee: LSI Corporation, Milpitas, CA (US)
`
`(73)
`
`(*)
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21)
`
`Appl. No.: 13/252,632
`
`(22)
`
`Filed:
`
`Oct. 4, 2011
`
`(65)
`
`Prior Publication Data
`US 2012/OO21599 A1
`Jan. 26, 2012
`
`(62)
`
`(51)
`
`(52)
`(58)
`
`Related U.S. Application Data
`Division of application No. 1 1/277,188, filed on Mar.
`22, 2006, now Pat. No. 8,049,340.
`
`Int. Cl.
`(2006.01)
`HOIL 2L/21763
`U.S. Cl. ................. 438/622: 257/758; 257/E21.536
`Field of Classification Search ........................ None
`See application file for complete search history.
`
`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`6,075,700 A
`6/2000 Houghton et al.
`6,392,301 B1
`5, 2002 Waizman et al.
`6,397,375 B1
`5, 2002 Block et al.
`6,430,030 B1
`8/2002 Farooq et al.
`6,872.921 B1
`3/2005 DeCobert et al.
`6,875,921 B1
`4/2005 Conn
`7,358,609 B2
`4/2008 Iguchi et al.
`2002/0027282 A1
`3/2002 Kawakami et al.
`2002.00437.15 A1
`4/2002 Takizawa
`2004/0021218 A1
`2/2004 Hayama et al.
`2004/0227227 A1 11/2004 Imanaka et al.
`2005/OO376O1 A1
`2/2005 Hsu et al.
`2005/0200022 A1
`9, 2005 Seto
`Primary Examiner — Wael Fahmy
`Assistant Examiner — Sarah Salerno
`(74) Attorney, Agent, or Firm — Otterstedt, Ellenbogen &
`Kammer, LLP
`
`ABSTRACT
`(57)
`An integrated circuit package substrate includes a first and an
`additional electrically conductive layer separated from each
`other by an electrically insulating layer, a contact pad formed
`in the first electrically conductive layer for making a direct
`connection between the integrated circuit package substrate
`and a printed circuit board, and a cutout formed in the addi
`tional electrically conductive layer wherein the cutout
`encloses an area that completely Surrounds the contact pad for
`avoiding parasitic capacitance between the additional electri
`cally conductive layer and the printed circuit board.
`20 Claims, 6 Drawing Sheets
`
`
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`500 <
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`E.
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`DE BUMPS
`BUMPPAD
`
`
`
`A. E. OREEdo E.
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`506
`f 12
`504
`1 10
`5O2
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`12O
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`

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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 3 of 12 PageID #: 125
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`U.S. Patent
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`Oct. 16, 2012
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`Sheet 1 of 6
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`US 8,288,269 B2
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`iš
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`FIG, (PRIORART
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`

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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 4 of 12 PageID #: 126
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`U.S. Patent
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`Oct. 16, 2012
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`Sheet 2 of 6
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`US 8,288,269 B2
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`2
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`4 (PRIOR ART)
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`Layer 4
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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 5 of 12 PageID #: 127
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`U.S. Patent
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`Oct. 16, 2012
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`Sheet 3 of 6
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`US 8,288,269 B2
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`909
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`Z || ||
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`ZOG
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`009
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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 6 of 12 PageID #: 128
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`U.S. Patent
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`Oct. 16, 2012
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`Sheet 4 of 6
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`US 8,288,269 B2
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`6OO Y
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`FIG. 6
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`7OO Y
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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 7 of 12 PageID #: 129
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`U.S. Patent
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`Oct. 16, 2012
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`Sheet 5 of 6
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`US 8,288,269 B2
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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 8 of 12 PageID #: 130
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`U.S. Patent
`
`Oct. 16, 2012
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`Sheet 6 of 6
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`US 8,288,269 B2
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`
`
`FORMA FIRST AND AN ADDITIONAL ELECTRICALLY
`CONDUCTIVE LAYER SEPARATED FROM EACH OTHER BY
`ANELECTRICALLY INSULATING LAYER IN AN INTEGRATED
`CIRCUIT PACKAGE SUBSTRATE
`
`FORMA CONTACT PAD IN THE FIRST ELECTRICALLY
`CONDUCTIVE LAYER FOR MAKING A DIRECT CONNECTION
`BETWEEN THE INTEGRATED CIRCUIT PACKAGE
`SUBSTRATE AND AN INTEGRATED CIRCUIT DE
`
`FORM A CUTOUT IN THE ADDITIONAL ELECTRICALLY
`CONDUCTIVE LAYER TO ENCLOSE AN AREA THAT COMPLETELY
`SURROUNDS THE CONTACT PAD TO AVOD PARASITIC
`CAPACITANCE BETWEEN THE ADDITIONAL ELECTRICALLY
`CONDUCTIVE LAYER AND THE PRINTED CIRCUIT BOARD
`
`908
`
`FIG. 9
`
`

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`Case 2:20-cv-00048-JRG Document 1-2 Filed 02/21/20 Page 9 of 12 PageID #: 131
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`US 8,288,269 B2
`
`1.
`METHODS FORAVOIDING PARASITIC
`CAPACITANCE IN AN INTEGRATED
`CIRCUIT PACKAGE
`
`CROSS-REFERENCE TO RELATED
`APPLICATIONS
`
`This application is a divisional of U.S. application Ser. No.
`1 1/277,188, filed on Mar. 22, 2006, the disclosure of which is
`incorporated herein by reference in its entirety for all pur
`poses.
`
`10
`
`BACKGROUND OF THE INVENTION
`
`2
`with the following drawings presented by way of example and
`not limitation, wherein like references indicate similar ele
`ments throughout the several views of the drawings, and
`wherein:
`FIG. 1 illustrates a simplified partial side view of a typical
`ball grid array (BGA) integrated circuit package substrate of
`the prior art;
`FIG. 2 illustrates a top view of the contact pad metal layer
`in the integrated circuit package Substrate of FIG. 1;
`FIG.3 illustrates a top view of the routing metal layer in the
`integrated circuit package Substrate of FIG. 1;
`FIG. 4 illustrates a top view of the ground return metal
`layer in the integrated circuit package Substrate of FIG. 1;
`FIG. 5 illustrates a simplified partial side view of an inte
`grated circuit package substrate that includes a cutout formed
`in a routing metal layer and in a ground metal layer that
`completely Surrounds a contact pad in the contact pad metal
`layer to reduce parasitic capacitance;
`FIG. 6 illustrates a top view of the contact pad metal layer
`in the integrated circuit package of FIG. 5;
`FIG. 7 illustrates a top view of the routing metal layer in the
`integrated circuit package substrate of FIG. 5;
`FIG. 8 illustrates a top view of the ground return metal
`layer in the integrated circuit package substrate of FIG. 5; and
`FIG. 9 illustrates a flow chart for a method of avoiding
`parasitic capacitance in an integrated circuit package Sub
`Strate.
`Elements in the figures are illustrated for simplicity and
`clarity and have not necessarily been drawn to scale. For
`example, the dimensions, sizing, and/or relative placement of
`Some of the elements in the figures may be exaggerated rela
`tive to other elements to clarify distinctive features of the
`illustrated embodiments. Also, common but well-understood
`elements that may be useful or necessary in a commercially
`feasible embodiment are often not depicted in order to facili
`tate a less obstructed view of the illustrated embodiments.
`
`1. Field of the Invention
`The present invention is directed to the design and manu
`facture of integrated circuits. More specifically, but without
`limitation thereto, the present invention is directed to the
`design of an integrated circuit package that minimizes para
`sitic capacitance between metal layers in a ball grid array
`integrated circuit package.
`2. Description of Related Art
`An integrated circuit package commonly includes several
`electrically conductive planar layers separated from one
`another by electrically insulating layers. Connections
`between the electrically conductive layers, typically metal
`layers, are made by forming vias in the electrically insulating
`layers, typically dielectric layers, and depositing an electri
`cally conductive material in the Vias, such as copper. Circuits
`are formed in the metal layers by etching away a portion of the
`metal, for example, to form traces in routing metal layers and
`contacts in contact pad metal layers. The contact pads are
`used to make electrical connection between the integrated
`circuit package and a printed circuit board. Some metal layers
`in the integrated circuit package are used to conduct a Voltage
`Supply and others to conduct a ground return to the routing
`metal layers and the contact pad metal layers.
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`SUMMARY OF THE INVENTION
`
`In one embodiment, an integrated circuit package Substrate
`includes:
`a first and an additional electrically conductive layer sepa
`rated from each other by an electrically insulating layer,
`a contact pad formed in the first electrically conductive
`layer for making a direct connection between the integrated
`circuit package Substrate and a printed circuit board; and
`a cutout formed in the additional electrically conductive
`layer wherein the cutout encloses an area that completely
`Surrounds the contact pad for avoiding parasitic capacitance
`between the additional electrically conductive layer and the
`printed circuit board.
`In another embodiment, a method includes steps of
`(a) forming a first and an additional electrically conductive
`layer separated from each other by an electrically insulating
`layer in an integrated circuit package Substrate;
`(b) forming a contact pad in the first electrically conductive
`layer for making a direct connection between the integrated
`circuit package Substrate and a printed circuit board; and
`(c) forming a cutout in the additional electrically conduc
`tive layer wherein the cutout encloses an area that completely
`covers the contact pad for avoiding parasitic capacitance
`between the additional electrically conductive layer and the
`printed circuit board.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`The above and other aspects, features and advantages will
`become more apparent from the description in conjunction
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`DESCRIPTION OF THE ILLUSTRATED
`EMBODIMENTS
`
`The following description is not to be taken in a limiting
`sense, rather for the purpose of describing by specific
`examples the general principles that are incorporated into the
`illustrated embodiments. For example, certain actions or
`steps may be described or depicted in a specific order to be
`performed. However, practitioners of the art will understand
`that the specific order is only given by way of example and
`that the specific order does not exclude performing the
`described steps in another order to achieve substantially the
`same result. Also, the terms and expressions used in the
`description have the ordinary meanings accorded to Such
`terms and expressions in the corresponding respective areas
`of inquiry and study except where other meanings have been
`specifically set forth herein.
`In integrated circuits such as serializer/deserializer (SER
`DES) devices that convert a serial data stream to or from a
`parallel data stream, high data transfer rates may require fast
`Switching speeds that Surpass 1 GHz. At Such high frequen
`cies, the parasitic capacitance between transmit (TX) and
`receive (RX) contact pads in the contact pad layer and nearby
`metal layers of the integrated circuit package may result in a
`deterioration of the signal waveform and a correspondingly
`reduced circuit performance.
`FIG. 1 illustrates a simplified partial side view of a typical
`ball grid array (BGA) integrated circuit package substrate
`100 of the prior art. Shown in FIG. 1 are a contact pad metal
`layer 102, a routing metal layer 104, a ground return metal
`
`

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`US 8,288,269 B2
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`4
`In one embodiment, an integrated circuit package substrate
`includes:
`a first and an additional electrically conductive layer sepa
`rated from each other by an electrically insulating layer,
`a contact pad formed in the first electrically conductive
`layer for making a direct connection between the integrated
`circuit package Substrate and a printed circuit board; and
`a cutout formed in the additional electrically conductive
`layer wherein the cutout encloses an area that completely
`Surrounds the contact pad for avoiding parasitic capacitance
`between the additional electrically conductive layer and the
`printed circuit board.
`FIG. 5 illustrates a simplified partial side view of an inte
`grated circuit package substrate 500 that includes a cutout
`formed in a routing metal layer and in a ground metal layer
`that completely surrounds a contact pad in the contact pad
`metal layer to reduce parasitic capacitance. Shown in FIG. 5
`are a ball pad 108, dielectric layers 110 and 112, vias 118, a
`printed circuit board 120, a contact pad metal layer 502, a
`routing metal layer 504, a ground return metal layer 506,
`cutouts 508, cutout areas 510, and parasitic capacitances 512
`and 514.
`In the example of FIG. 5, the integrated circuit package
`substrate 500 may be made in the same manner as in FIG. 1,
`except that the cutout 508 is formed in the routing metal layer
`504 and in the ground return metal layer 506 under the ball
`pad 108. The cutout 508 may be formed, for example, in the
`same manner used to remove metal in the routing metal layer
`104 around the traces 302 in FIG. 3. The cutout 508 may be
`included in the floorplan of the integrated circuit design
`according to well-known techniques to avoid routing con
`flicts. For example the cutout area 510 may include a routing
`trace for connecting a via between the ball pad 108 and the
`routing metal layer 504.
`The cutout 508 encloses the cutout area 510 so that the area
`enclosed by the ball pad 108 is completely surrounded by the
`cutout area 510. In other words, there is no overlap between
`the area enclosed by the ball pad 108 and the metal in the
`routing metal layer 504 and in the ground return metal layer
`506 above the ball pad 108. In one embodiment, the cutout
`508 has the same dimensions as the ball pad 108. In other
`embodiments, the cutout 508 is larger than the ball pad 108.
`The ball pad 108 may be any type of contact pad used to make
`electrical connection between the integrated circuit package
`500 and a printed circuit board. For example, the ball pad 108
`may be a contact used to make electrical connection between
`the integrated circuit package 500 and a printed circuit board
`for a ball grid array (BGA) integrated circuit, a flip-chip
`integrated circuit, a wirebond integrated circuit, a single in
`line package, or a micro-chip module. In another embodi
`ment, the ball pad 108 may be an electrically conductive area
`in any metal layer for which a reduced parasitic capacitance
`between the metal layer and the printed circuit board is
`desired.
`The dashed lines in FIG.5 extending upward from the sides
`of the contact pad 108 enclose the areas of the routing metal
`layer 504 and the ground return metal layer 506 that are
`overlapped by the ball pad 108. Because the cutouts 508
`completely surround the areas of the routing metal layer 504
`and the ground return metal layer 506 that are overlapped by
`the ball pad 108, the area enclosed by the ball pad 108 does
`not overlap the metal in the routing metal layer 504 or the
`ground return metal layer 506. As a result, the parasitic
`capacitances 512 and 514 are approximately 16 percent or
`more lower than the parasitic capacitances 114 and 116 in
`FIG.1. The reduction in parasitic capacitance advantageously
`
`3
`layer 106, a ball pad 108, dielectric layers 110 and 112,
`parasitic capacitances 114 and 116, and a printed circuit
`board 120.
`In the example of FIG. 1, the contact pad metal layer 102,
`the routing metal layer 104, and the ground return metal layer
`106 are electrically conductive layers made of for example,
`copper or copper alloy. The dielectric layers 110 and 112 are
`electrically insulating layers made of for example, an epoxy
`compound. The ball pad 108 is formed in the contact pad
`metal layer 102 to connect the integrated circuit package
`substrate 100 to the printed circuit board 120, typically by
`vias (not shown). Vias are holes in the dielectric layers 110
`and 112 that are filled with an electrically conductive mate
`rial. Such as copper, to make electrical connections between
`the contact pad metal layer 102, the routing metal layer 104,
`and the ground return metal layer 106.
`Metal layers that have a relatively large metal area may
`produce significant parasitic capacitance. For example, the
`parasitic capacitance 114 between the ball pad 108 and the
`routing metal layer 104 and the parasitic capacitance 116
`between the underlying ball pad 108 and the ground return
`metal layer 106 have been found by the inventors to produce
`distortion of the Switching waveform of high-frequency sig
`nals used, for example, in serializing/deserializing devices
`(SERDES). As a result, the maximum operating frequency
`that may be used in the integrated circuit is disadvantageously
`limited by the parasitic capacitances 114 and 116 in the inte
`grated circuit package Substrate 100.
`FIG. 2 illustrates a top view 200 of the contact pad metal
`layer 102 in the integrated circuit package substrate of FIG.1.
`Shown in FIG. 2 are ball pads 108, vias 118, transmit (TX)
`rows 202, and receive (RX) rows 204.
`In FIG. 2, the ball pads 108 included in the transmit (Tx)
`rows 202 and the receive (RX) rows 204 are typically driven
`by high-frequency signals in excess of 1 GHz.
`FIG. 3 illustrates a top view 300 of the routing metal layer
`104 in the integrated circuit package substrate of FIG. 1.
`Shown in FIG.3 are vias 118, transmit (Tx) rows 202, receive
`(RX) rows 204, and routing traces 302.
`In FIG. 3, the vias 118 connect the ball pads 108 in the
`contact pad metal layer 102 in FIG.1 to the routing traces 302.
`Some of the metal in the routing metal layer 104 is removed
`around the routing traces 302; however, the area of the ball
`pads 108 in FIG.1 constituting the transmit (Tx) rows 202 and
`the receive (RX) rows 204 in FIG. 2 still overlaps the metal
`substantially in the routing metal layer 104, resulting in the
`parasitic capacitance 114 between the contact pad metal layer
`102 and the routing metal layer 104 in FIG. 1.
`FIG. 4 illustrates a top view 400 of the ground return metal
`layer 106 in the integrated circuit package substrate of FIG.1.
`Shown in FIG. 4 are transmit (Tx) rows 202, receive (RX)
`rows 204, and routing traces 402.
`In FIG. 4, some of the metal in the routing metal layer 104
`is removed around the routing traces 402; however, the area of
`the ball pads 108 in FIG. 1 constituting the transmit (Tx) rows
`202 and the receive (RX) rows 204 in FIG. 2 still overlaps the
`metal substantially in the routing metal layer 106, resulting in
`the parasitic capacitance 116 between the contact pad metal
`layer 102 and the ground return metal layer 106 in FIG. 1.
`The parasitic capacitance between the contact pads in the
`contact pad metal layer 102 and other nearby metal layers of
`the integrated circuit package substrate may be advanta
`geously avoided by forming cutouts in each of the other metal
`layers to enclose an area that Surrounds each of the contact
`pads as described below.
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`FIG. 9 illustrates a flow chart for a method of avoiding
`parasitic capacitance in an integrated circuit package Sub
`Strate.
`Step 902 is the entry point for the flow chart 900.
`In step 904, a first and an additional electrically conductive
`layer separated from each other by an electrically insulating
`layer are formed in an integrated circuit package substrate
`according to well-known techniques. For example, the first
`electrically conductive layer may be a contact pad metal layer.
`In step 906, a contact pad is formed in the first electrically
`conductive layer for making a direct connection between the
`integrated circuit package Substrate and a printed circuit
`board according to well-known techniques. For example, the
`contact pad may be a ball pad used to make electrical con
`nection between the integrated circuit package and a printed
`circuit board for a ball grid array (BGA) integrated circuit, a
`flip-chip integrated circuit, a wirebond integrated circuit, a
`single in-line package, or a micro-chip module.
`In step 908, a cutout is formed in the additional electrically
`conductive layer. The cutout encloses an area that completely
`Surrounds the contact pad to avoid parasitic capacitance
`between the additional electrically conductive layer and the
`printed circuit board. The additional electrically conductive
`layer may be, for example, a routing metal layer, a ground
`return metal layer, or a Voltage Supply metal layer.
`Step 910 is the exit point of the flow chart 900.
`Although the flowchart description above is described and
`shown with reference to specific steps performed in a specific
`order, these steps may be combined, sub-divided, or reor
`dered without departing from the scope of the claims. Unless
`specifically indicated, the order and grouping of steps is not a
`limitation of other embodiments that may lie within the scope
`of the claims.
`The specific embodiments and applications thereof
`described above are for illustrative purposes only and do not
`preclude modifications and variations that may be made
`within the scope of the following claims.
`What is claimed is:
`1. A method, comprising steps of
`forming a first electrically conductive layer including a
`plurality of rows of contact pads;
`forming an electrically insulating layer on the first electri
`cally conductive layer; and
`forming a second electrically conductive layer over the
`electrically insulating layer Such that there is no inter
`mediate conductive layer between the first and second
`electrically conductive layers, the second electrically
`conductive layer comprising metal and a plurality of
`cutouts wherein each cutout encloses an electrically
`insulating area within the second electrically conductive
`layer and wherein each electrically insulating area com
`pletely overlaps a corresponding one of the contact pads
`such that there is substantially no overlap of the rows of
`contact pads with metal in the second electrically con
`ductive layer.
`2. The method of claim 1, further comprising:
`forming the contact pads as transmit and receive rows of
`contact pads;
`forming the second electrically conductive layer as a rout
`ing layer including routing traces such that the contact
`pads are operable with the second electrically conduc
`tive layer for converting a serial data stream to or from a
`parallel data stream; and
`forming the cutouts in rows corresponding to and aligned
`with the rows of contact pads.
`3. The method of claim 1, wherein the cutouts have the
`same dimensions as the contact pads.
`
`5
`extends the upper frequency limit that may be used to drive
`the ball pad 108 in the integrated circuit package substrate
`SOO.
`In another embodiment, the area enclosed by the ball pad
`108 may partially overlap the metal in the routing metal layer
`504 or the ground return metal layer 506 to reduce the para
`sitic capacitances 512 and 514 by a selected minimum limit.
`For example, the selected minimum limit may be 10 percent
`less than the parasitic capacitances 114 and 116 in FIG. 1.
`In the example of FIG. 5, only three electrically conductive
`layers are included; however, other embodiments may
`include a different number of electrically conductive layers.
`For example, another embodiment may include a 10-layer
`buildup having contact pads formed in metal layer 10 (M10)
`and cutouts formed in metal layers M9, M8, M7, and M6. The
`number of electrically conductive layers in which cutouts are
`formed depends on the proximity of the additional electri
`cally conductive layers to the first electrically conductive
`layer. The closer the proximity of the additional electrically
`conductive layers to the first electrically conductive layer, the
`greater the number of additional electrically conductive lay
`ers that may advantageously include the cutouts to minimize
`the parasitic capacitance between the contact pads and the
`other metal layers.
`FIG. 6 illustrates a top view 600 of the contact pad metal
`layer 502 for the integrated circuit package of FIG. 5. Shown
`in FIG. 6 are ball pads 108, vias 118, transmit (Tx) rows 602,
`and receive (RX) rows 604. The contact pad metal layer 502
`may be made, for example, in the same manner as the contact
`pad metal layer 102 in FIG. 1.
`FIG. 7 illustrates a top view 700 of the routing metal layer
`504 in the integrated circuit package substrate of FIG. 5.
`Shown in FIG. 7 are transmit (Tx) rows 602, receive (RX)
`rows 604, routing traces 702, cutouts 704, and vias 118.
`In FIG. 7, the vias 118 connect the ball pads 108 in the
`contact pad metal layer 502 in FIG.5 to the routing traces 702.
`In addition to the metal in the routing metal layer 504 that is
`removed around the routing traces 702, the cutouts 704 com
`pletely surround the area enclosed by the ball pads 108 in
`FIG. 5 constituting the transmit (Tx) rows 602 and the receive
`(RX) rows 604 in FIG. 6, resulting in the reduced parasitic
`capacitance 512 between the contact pad layer 502 and the
`routing metal layer 504 in FIG. 5.
`FIG. 8 illustrates a top view 800 of the ground return metal
`layer 506 for the integrated circuit package substrate of FIG.
`5. Shown in FIG. 8 are transmit (Tx) rows 602, receive (RX)
`rows 604, and cutouts 802.
`In FIG. 8, the cutouts 802 completely surround the area
`enclosed by the ball pads 108 in FIG. 5 constituting the
`transmit (Tx) rows 602 and the receive (RX) rows 604 in FIG.
`6, resulting in the reduced parasitic capacitance 514 between
`the contact pad layer 502 and the ground return metal layer
`SO6 in FIG.S.
`In another embodiment, a method of avoiding parasitic
`capacitance in an integrated circuit package substrate
`includes steps of
`(a) forming a first and an additional electrically conductive
`layer separated from each other by an electrically insulating
`layer in an integrated circuit package Substrate;
`(b) forming a contact pad in the first electrically conductive
`layer for making a direct connection between the integrated
`circuit package Substrate and a printed circuit board; and
`(c) forming a cutout in the additional electrically conduc
`tive layer wherein the cutout encloses an area that completely
`Surrounds the contact pad for avoiding parasitic capacitance
`between the additional electrically conductive layer and the
`printed circuit board.
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`5
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`10
`
`15
`
`8
`forming a plurality of electrically conductive layers imme
`diately proximate the first electrically conductive layer,
`each of the electrically conductive layers including a
`plurality of electrically insulating areas Such that there is
`substantially no overlap of the rows of contact pads with
`metal in the plurality of electrically conductive layers;
`and
`forming a plurality of dielectric layers separating, respec
`tively, the electrically conductive layers and the first
`layer from each other.
`11. The method of claim 10, further comprising forming a
`plurality of rows of cutouts in each of the electrically conduc
`tive layers corresponding to and aligned with the rows of
`electrical contacts, each of the cutouts enclosing one of the
`electrically insulating areas.
`12. The method of claim 11, wherein one of the electrically
`conductive layers is a routing metal layer including routing
`traces.
`13. The method of claim 11, further comprising forming
`the cutouts to completely overlap corresponding electrical
`COntactS.
`14. The method of claim 11, further comprising:
`forming the electrical contacts as transmit and receive rows
`of contact pads; and
`forming vias connecting the contact pads with one of the
`electrically conductive layers.
`15. The method of claim 14, further comprising forming
`one of the electrically conductive layers as a routing layer
`comprising routing traces and another of the electrically con
`ductive layers as a ground return metal layer.
`16. The method of claim 15, further comprising electrically
`connecting the contact pads to a printed circuit board.
`17. The method of claim 11, further comprising electrically
`connecting the electrical contacts to a printed circuit board.
`18. The method of claim 17, further comprising forming
`the cutouts to completely overlap corresponding electrical
`COntactS.
`19. The method of claim 18, further comprising:
`forming the electrical contacts in transmit and receive
`rows; and
`forming vias connecting the electrical contacts with one of
`the electrically conductive layers.
`20. The method of claim 11, further comprising forming
`the cutouts to completely overlap corresponding electrical
`COntactS.
`
`7
`4. The method of claim 1, further comprising:
`forming a third electrically conductive layer comprising
`metal and a plurality of cutouts above the second elec
`trically conductive layer, and
`forming a second electrically insulating layer between the
`second and third electrically conductive layers, each of
`the cutouts in the third electrically conductive layer
`enclosing an electrically insulating area within the third
`electrically conductive layer such that there is substan
`tially no overlap of the rows of contact pads with metal
`in the third electrically conductive layer.
`5. The method of claim 4, further comprising:
`forming the third electrically conductive layer as a ground
`return metal layer; and
`forming the second electrically conductive layer as a rout
`ing metal layer electrically connected to the first electri
`cally conductive layer.
`6. The method of claim 1, further comprising:
`forming the second electrically conductive layer as a rout
`ing layer including routing traces; and
`forming the cutouts in rows corresponding to and aligned
`with the rows of contact pads.
`7. The method of claim 1, further comprising:
`forming a third electrically conductive layer comprising
`metal and including rows of cutouts, each of the cutouts
`in the third electrically conductive layer enclosing an
`electrically insulating layer in the third electrically con
`ductive layer, and
`forming a second electrically insulating layer between the
`second and third electrically conductive layers, wherein
`the rows of cutouts in the third electrically conductive
`layer correspond to and are aligned with the rows of
`contact pads such that there is Substantially no overlap of
`the rows of contact pads with metal in the third electri
`cally conductive layer and there is no intermediate con
`ductive layer between the third electrically conductive
`layer and the first electrically conductive layer other than
`the second electrically conductive layer.
`8. The method of claim 7, wherein the second electrically
`conductive layer is a routing metal layer and the third elec
`trically conductive layer is a ground plane layer.
`9. The method of claim 1, further including electrically
`connecting the first electrically conductive layer to a printed
`circuit board.
`10. A method, comprising steps of
`forming a first layer including a plurality of rows of elec
`trical contacts;
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`25
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`30
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`35
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`40
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`45
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