Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 1 of 9 PageID #: 181
`Case 2:20-cv-00048—JRG Document 1-7 Filed 02/21/20 Page 1 of 9 PageID #: 181
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`EXHIBIT G
`EXHIBIT G
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`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 2 of 9 PageID #: 182
`
`(12) United States Patent
`Banerjee et al.
`
`USOO6707132B1
`(10) Patent No.:
`US 6,707,132 B1
`(45) Date of Patent:
`Mar. 16, 2004
`
`(54) HIGH PERFORMANCE SI-GE DEVICE
`MODULE WITH CMOS TECHNOLOGY
`
`(75) Inventors: Robi Banerjee, Gresham, OR (US);
`Derryl J. Allman, Camas, WA (US);
`David T. Price, Gresham, OR (US)
`(73) Assignee: LSI Logic Corporation, Milpitas, CA
`(US)
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(*) Notice:
`
`(21) Appl. No.: 10/288,410
`1-1.
`(22) Filed:
`Nov. 5, 2002
`(51) Int. Cl." .............................................. H01L31/117
`(52) U.S. Cl. ................
`... 257/616; 257/18: 257/19
`(58) Field of Search
`257/616, 18, 19
`
`- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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`s u-s-s
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`(56)
`
`References Cited
`
`U.S. PATENT DOCUMENTS
`5,357,119 A * 10/1994 Wang et al. .................. 257/18
`5,906,708 A * 5/1999 Robinson et al. ........... 438/694
`6,555.839 B2 * 4/2003 Fitzgerald .................... 257/18
`
`
`
`2003/O122154 A1
`* cited by examiner
`
`7/2003 Babcock et al. ............ 257/197
`
`Bushnell,
`
`Primary Examiner—David Nelms
`Assistant Examiner-Tu-Tu Hot
`(74) Attorney, Agent, or Firm Trexler,
`Giangiori, BlackStone & Marr, Ltd.
`(57)
`ABSTRACT
`A semiconductor device wherein some parts of a circuit are
`disposed on Si-Ge regions and others are implemented in
`Silicon Substrate regions of the chip. The Si-Ge region
`provides that carrier flow is forced to the Surface channel
`region which helps reduce Short channel effects. A method
`of making Such a Semiconductor device is also provided and
`includes Steps of forming a thermal oxide layer on a Silicon
`Substrate, masking at least a portion of the thermal oxide
`lay
`ing at least a portion of the thermal oxide lay
`ayer, removing at least a portion of the thermal OXide layer
`in order to expose a portion of the Silicon Substrate, epi
`the Silicon Substrate, epitaxially growing a Silicon layer on
`p
`y g
`9.
`y
`the Si-Ge layer, and continuing manufacture of the device
`by forming a circuit on the Si-Ge regions and non-Si-Ge
`regions of the Semiconductor device.
`
`taxially growing an Si-Ge layer on the exposed portion of
`
`18 Claims, 4 Drawing Sheets
`
`

`

`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 3 of 9 PageID #: 183
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`U.S. Patent
`
`Mar. 16, 2004
`
`Sheet 1 of 4
`
`US 6,707,132 B1
`
`Standard CMOS Process r30
`40
`
`
`
`
`
`Grow Thermal Pad/Screen
`Silicon Dioxide and Silicon
`Nitride (or Poly)
`50
`Photoresist App.
`60, 70
`Etching Steps
`80
`Fil Trenches, COver
`Trans. Regions
`90
`
`"Planarize" Surface
`
`100
`Remove Silicon
`Nitride and Oxide
`
`w
`
`110
`
`Selective Exp. Growth / Dep.
`2O
`Grow / Dep. Gate Ox, / Sil.
`Nitride Layer
`
`f 30
`
`FIG. 1
`
`

`

`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 4 of 9 PageID #: 184
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`U.S. Patent
`
`Mar. 16, 2004
`
`Sheet 2 of 4
`
`US 6,707,132 B1
`
`32
`
`33
`
`34
`
`
`
`FIG.2
`
`

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`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 5 of 9 PageID #: 185
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`U.S. Patent
`
`Mar. 16, 2004
`
`Sheet 3 of 4
`
`US 6,707,132 B1
`
`43
`
`43
`
`43
`
`34
`
`FIG.8
`
`
`
`43
`
`

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`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 6 of 9 PageID #: 186
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`U.S. Patent
`
`Mar. 16, 2004
`
`Sheet 4 of 4
`
`US 6,707,132 B1
`
`
`
`

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`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 7 of 9 PageID #: 187
`
`1
`HIGH PERFORMANCE S-GE DEVICE
`MODULE WITH CMOS TECHNOLOGY
`
`US 6,707,132 B1
`
`BACKGROUND
`The present invention generally relates to Semiconductor
`proceSS integration, and more specifically relates to a Semi
`conductor device which has Si-Ge on Silicon, and a
`method of making a Semiconductor device where the
`method includes depositing Si-Ge on Silicon.
`The Semiconductor industry has been constantly Striving
`to improve the performance of Semiconductor devices (i.e.,
`Semiconductor products). To date, various Schemes and
`improvements have been proposed, both in the area of
`proceSS technology and circuit design, in order to improve
`Speed, reduce power consumption, or otherwise improve
`performance.
`Present Semiconductor devices are typically configured
`Such that FET transistors and other devices, Such as Speed
`performance Sensitive parts of a circuit, are disposed on
`Silicon. The Scaling of transistors to Smaller dimensions for
`reduced die size, increased logic functionality and reduced
`power has resulted in a decrease in the operational perfor
`mance of a transistor. The drop in transistor drive currents
`reduces the performance of a circuit and increases the
`dynamic power consumption. The reduction in the drive
`current results from a decrease in the mobility of the electron
`due to increased Surface and impurity Scattering in the
`Surface channel of the device.
`
`1O
`
`15
`
`25
`
`OBJECTS AND SUMMARY
`A general object of an embodiment of the present inven
`tion is to provide a Semiconductor device which has at least
`a region that provides Si-Ge on Silicon.
`Another object of an embodiment of the present invention
`is to provide a method of making a Semiconductor device,
`where the method includes depositing Si-Ge on Silicon.
`Still another object of an embodiment of the present
`invention is to provide a Semiconductor device which is
`configured Such that carrier flow is confined or near the
`Surface of the device.
`Still yet another object of an embodiment of the present
`invention is to provide a Semiconductor device which is
`configured Such that it reduces leakage and power consump
`tion.
`Yet still another object of an embodiment of the present
`invention is to provide a Semiconductor device which is
`configured Such that electron hole carrier mobility is
`improved, thereby resulting in improved transistor perfor
`CC.
`Briefly, and in accordance with at least one of the forgoing
`objects, an embodiment of the present invention provides a
`Semiconductor device which has at least a region where
`Si-Ge is disposed on Silicon. Specifically, the Semicon
`ductor device preferably includes Si-Ge disposed on a
`Silicon Substrate. The Semiconductor device may include a
`Silicon region which does not include any Si-Ge, but
`preferably also includes an Si-Ge region which includes
`Si-Ge on Silicon. While the Silicon region includes a
`thermal oxide layer, the Si-Ge region does not. Preferably,
`the Si-Ge is provided as an Si-Gelayer which is disposed
`between a Silicon layer and the Silicon substrate. Ideally,
`there is at least one circuit device or circuitry on the Silicon
`region and at least one circuit device or circuitry on the
`Si-Ge region. The lattice Structure in the Silicon layer
`
`35
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`40
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`45
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`50
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`55
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`60
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`65
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`2
`grown above the Si-Ge layer is strained due to the lattice
`mismatch between the epitaxial Si-Ge and Siregions. This
`Strained Silicon layer results in less electron Scattering,
`which improves electron mobility and results in improved
`transistor Switching Speed and lower dynamic power con
`Sumption. These layers of Germanium doped Silicon and
`Strained silicon do not have to be selectively grown on the
`Surface of the exposed Substrate. These films can be grown
`on the Surface of the exposed Substrate and at the same time
`depositing a poly crystalline version of the film on the
`surface above the silicon dioxide layers. The thickness of
`these poly crystalline layers can be thinner or thicker than
`the epitaxial grown layers.
`A method of making Such a Semiconductor device is also
`provided, and includes Steps of forming a thermal oxide
`layer on a Silicon Substrate, masking at least a portion of the
`thermal oxide layer, removing (Such as by wet etching) at
`least a portion of the thermal oxide layer in order to expose
`a portion of the Silicon Substrate, epitaxially growing an
`Si-Ge layer selectively on the exposed portion of the
`Silicon Substrate using either undoped Si-Ge or Si-Ge
`doped with carbon, epitaxially growing a Silicon layer on
`the Si-Ge layer using either undoped Silicon or Silicon
`doped with nitrogen, and continuing manufacture of the
`device by forming a circuit on the Si-Ge regions and
`non-Si-Ge regions of the Semiconductor device.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`The organization and manner of the Structure and opera
`tion of the invention, together with further and advantages
`thereof, may best be understood by reference to the follow
`ing description, taken in connection with the accompanying
`drawings, wherein like reference numerals identify like
`elements in which:
`FIG. 1 is a block diagram of a method which is in
`accordance with an embodiment of the invention; and
`FIGS. 2-13 are general schematic view of a semiconduc
`tor device illustrating steps of the method shown in FIG. 1.
`Description
`While the invention may be susceptible to embodiment in
`different forms, there is shown in the drawings, and herein
`will be described in detail, specific embodiments with the
`understanding that the present disclosure is to be considered
`an exemplification of the principles of the invention, and is
`not intended to limit the invention to that as illustrated and
`described herein.
`FIG. 1 illustrates, in block diagram form, a method 10 of
`making a semiconductor device, and FIGS. 2-13 illustrate a
`Semiconductor device 20 being made in accordance with the
`steps shown in FIG. 1. Both the method 10 of making the
`Semiconductor device 20 and the Structure of the Semicon
`ductor device 20 itself are embodiments of the present
`invention.
`Generally, the method 10 shown in FIG. 1 includes the
`Step of depositing Si-Ge on Silicon. As a result, both
`Si-Ge regions 22 and Silicon regions 24 are formed on the
`semiconductor device 20 (see FIG. 13). This provides that
`Speed performance Sensitive parts of the circuit may be built
`on the Si-Ge region(s) within the die, while non-speed
`Sensitive designs or legacy designs on Silicon may be
`implemented in the Silicon region(s) on the chip.
`In addition to depositing Si-Ge on Silicon, Silicon is
`deposited on the Si-Ge. Due to lattice mismatch between
`Si-Ge and Silicon, the carrier mobility is improved,
`
`

`

`Case 2:20-cv-00048-JRG Document 1-7 Filed 02/21/20 Page 8 of 9 PageID #: 188
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`US 6,707,132 B1
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`3
`thereby improving the performance of the Semiconductor
`device. Specifically, higher electron hole carrier mobility
`results in improved Speed for logic circuit circuits of the
`Semiconductor device. Additionally, the Strain causes the
`carriers to be restricted to the surface Silicon layer. This
`improves short channel effects thereby reducing leakage and
`therefore Standby power consumption.
`The method 10 shown in FIG. 1 provides that initially
`there is standard CMOS process flow up to pattern Zero
`mask layer to define initial alignment marks (box 30 in FIG.
`1). Then, as shown in FIG. 2, a thermal oxide layer (SiO2)
`32 and Silicon Nitride (or Poly) layer (Si3N4) 33 is screened
`onto the Silicon Substrate 34 (box 40 in FIG. 1). Then, as
`shown in FIG. 3, there is a photoresist application and
`exposure (box 50 in FIG. 1; the resist is shown as part 52 in
`FIG. 3) to define where a transistor device will be placed
`54). Then, as shown in FIG. 4, the portion(s) of the thermal
`oxide layer 32 and silicon nitride layer 33 which have not
`been masked in the previous Step arm removed, Such as by
`plasma etching, thereby exposing the Silicon Substrate (box
`60 in FIG. 1).
`Subsequently, as shown in FIG. 5, the silicon 32 is etched
`to form trenches 37, and the photoresist 52 is removed (box
`70 in FIG. 1). Then, as shown in FIG. 6, the trenches 37 are
`filled and the transistor regions 41 are covered with Silicon
`dioxide 43, preferably using an HDP deposition method
`(box 80 in FIG. 1). A thin layer of thermal oxide can also be
`utilized prior to deposition to remove etch damage.
`Then, as shown in FIG. 7 (box 90 in FIG. 1), an oxide
`CMP polish is performed or the oxide is removed from the
`surface 44 to make it planar to the tops of the Silicon Nitride
`layers 33 above the transistor regions 41. Part of the Silicon
`Nitride is removed in the Oxide CMP polish.
`The following steps can be repeated to form either 1) Por
`N doped region, 2) regions of higher Ge doping, 3) regions
`of different nitrogen concentrations on the Surface of the
`exposed silicon regions. To accomplish this, the wafer can
`be masked So that only Some of the Silicon transistor regions
`will be exposed. To shield the previous SEG or deposited
`layer from the next, a capping layer of Silicon Nitride or
`Silicon dioxide can be deposited at the end of each deposi
`tion.
`FIGS. 8-13 shown the formation, for example, of a P
`type region. As shown in FIG. 8 (box 100 in FIG. 1), the
`Silicon Nitride and oxide layers are removed, such as by
`using a wet etch process, leaving the Surface of the oxide in
`the trench above the transistor island level.
`As shown in FIG. 9 (box 110 in FIG. 1), at this point a
`selective expitaxial growth (SECT) of the Si-Ge. Strained
`Silayers 51, 53, 55 can occur. The Si-Ge layer can be
`doped with Carbon (or Nitrogen) and put of the Strained Si
`layer can be doped with Nitrogen and Boron (graded as
`shown). Prior to starting the growth the surface of the
`exposed Silicon Substrate will be cleaned insitu using a
`hydrogen or HCL gas. This clean is a reduction of the
`passivating oxide on the Surface of the Silicon. The HCL gas
`can also be used to remove metallics.
`Optionally, the Si-Ge and Strained silicon layer does not
`have to be grown Selectively, this layer can be deposited.
`Where Silicon is exposed on the Substrate epitaxial growth
`will occur while over the silicon dioxide the deposited layer
`will be poly crystalline 61 (see FIG. 10). The thickness of
`this layer can be adjusted by deposition conditions (Thinner
`or slightly thicker than the epitaxial Silicon). This option
`allows for the formation of thin film transistors on the silicon
`dioxide Surface (higher Ge content is needed) or the poly
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`4
`crystalline layer can be etched to from local interconnect
`between transistors. Additionally, these poly crystalline
`regions can be used to form capacitors for DRAM or analog
`applications when the process is repeated to form regions of
`different doping concentrations on the Surface of the Sub
`Strate. Once again, the nitrogen doping of the Strained Silicon
`layer is optional.
`Optional Capacitor formation 63 is shown in FIG. 11. The
`capacitor 63 does not have to be only connected to the SEG
`regions but can be contacted later during either the metal
`ization Steps or during other SEG depositions.
`FIG. 12 shows the formation of the SEG regions and FIG.
`13 shows Subsequent formation of N type channel region. AS
`shown in FIG. 12 (box 120 in FIG. 1), following the
`formation of the SEG regions, the growth of a gate oxide or
`deposition of a thin silicon nitride layer 65 can occur. The
`gate oxide growth can occur after tho SEC growth in the
`reactor or in another tool. If different gate oxide thickness
`are desired on the Surface of the Substrate the wafer can be
`masked and additional nitrogen can be added to Selected
`regions by implantation. The implant is centered at the
`surface of the SEG layer Nitrogen retards the growth or the
`Silicon dioxide film and when incorporated in the Silicon
`dioxide acts as a barrier for boron diffusion out of the
`channel or from the gate electrode (formed later during the
`process).
`As shown in FIG. 13 (box 130 in FIG. 1), the next step is
`to post-form the P and N type channel regions (only an
`Ntype region is shown in FIG. 13) with different gate oxide
`regions across the Surface of the Substrate 34. Conventional
`Semiconductor proceSS StepS may be used to form the
`transistors, except that the time and temperature of the
`Source and drain dopant activation anneal temperatures must
`be kept short and low enough So that the Strained Silicon
`layer remains.
`The method provides a novel and Simple Scheme to
`integrate on-chip Selective area Si-Ge on Si for high
`performance surface FET (CMOS) devices. Advantages of
`the process include the fact that the use and integration
`allows circuit performance improvement as measured by
`Speed of circuit, while allowing the use of legacy non-SOI
`designs. For example, a SRAM memory block may be
`included in the Silicon regions of the chip, while the Speed
`performance Sensitive Logic circuit (state machine) maybe
`included in the Si-Ge on Silicon region. This enables both
`high-performance Si-Ge on Silicon and Standard Silicon
`based circuit designs to co-exist on a chip. Furthermore,
`power consumption is reduced, and the same performance
`can be obtained by running the logic part of the circuit at a
`lower Voltage. Still further, the method uses existing mate
`rial and equipment Set, yet provides an elegant integration
`Solution. Additionally, there is the option of incorporating
`high performance bipolar devices in the flow.
`While embodiments of the present invention are shown
`and described, it is envisioned that those skilled in the art
`may devise various modifications of the present invention
`without departing from the Spirit and Scope of the appended
`claims.
`What is claimed is:
`1. A Semiconductor device comprising:
`a Silicon Substrate; and
`Si-Ge on the Silicon Substrate;
`wherein Said Semiconductor device includes a Silicon
`region which does not include any Si-Ge, and
`includes a Si-Ge region which includes Si-Ge on the
`Silicon Substrate;
`
`

`

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`US 6,707,132 B1
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`S
`further comprising at least one circuit device on the
`Silicon region and at least one circuit device on the
`Si-Ge region.
`2. A Semiconductor device as defined in claim 1, further
`comprising a Silicon layer, wherein the Si-Ge on the
`Silicon Substrate forms a Si-Ge layer, said Silicon layer
`being disposed on the Si-Ge layer, Said Si-Ge layer being
`disposed between said Silicon substrate and said Silicon
`layer.
`3. A Semiconductor device as defined in claim 2, further
`comprising a poly crystalline region and a capacitor formed
`in Said poly crystalline region.
`4. A Semiconductor device as defined in claim 3, wherein
`the capacitor is connected to the Si-Ge.
`5. A method of making a
`Semiconductor device comprising;
`providing a Silicon Substrate: and
`depositing Si-Ge on the Silicon Substrate;
`further comprising forming a thermal oxide layer on the
`Silicon Substrate;
`further comprising masking at least a portion of the
`thermal oxide layer which is disposed on the Silicon
`Substrates,
`further comprising removing at least a portion of the
`thermal oxide layer which is disposed on the Silicon
`Substrate in order to expose a portion of the Silicon
`Substrate;
`further comprising forming a Si-Ge layer on the exposed
`portion of the Silicon Substrate.
`6. A method as defined in claim 5, further comprising
`forming a Silicon layer on the Si-Ge layer which is
`disposed on the Silicon substrate.
`7. A method as defined in claim 6, wherein the step of
`forming a Silicon layer on the Si-Ge layer comprises
`epitaxially growing the Silicon layer.
`
`15
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`8. A method as defined in claim 7, further comprising
`epitaxially growing the Silicon layer using Silicon doped
`with nitrogen.
`9. A method as defined in claim 7, further comprising
`forming a poly crystalline region and forming a capacitor in
`Said poly crystalline region.
`10. A method as defined in claim 9, further comprising
`connecting the capacitor to the Si-Ge.
`11. A method as defined in claim 6, wherein the step of
`forming the Silicon layer on the Si-Ge layer comprises
`forming the Silicon layer such that the Silicon layer has a
`thickness of less than 100 A.
`12. A method as defined in claim 5, wherein the step of
`forming a Si-Ge layer on the exposed portion of the Silicon
`Substrate comprises epitaxially growing the Si-Ge layer.
`13. A method as defined in claim 12, further comprising
`epitaxially growing the Si-Ge layer using undoped
`Si-Ge.
`14. A method as defined in claim 12, further comprising
`epitaxially growing the Si-Ge layer using Si-Ge doped
`with carbon.
`15. A method as defined in claim 14, further comprising
`epitaxially growing the Si-Ge layer using Si-Ge doped
`with 0.2 to 1.5 atm 76 of carbon.
`16. A method as defined in claim 5, wherein the step of
`removing at least a portion of the thermal oxide layer
`comprising wet etching the portion of the thermal oxide
`layer.
`17. A method as defined in claim 5, further comprising
`forming a poly crystalline region and forming a capacitor in
`Said poly crystalline region.
`18. A method as defined in claim 17, further comprising
`connecting the capacitor to the Si-Ge.
`
`k
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`k
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`k
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`k
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`k
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