Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 1 of 17 PageID #: 201
`Case 2:20-cv-00048—JRG Document 1-9 Filed 02/21/20 Page 1 of 17 PageID #: 201
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`EXHIBIT I
`EXHIBIT I
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`

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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 2 of 17 PageID #: 202
`
`(12) United States Patent
`Chen et al.
`
`USOO6492712B1
`(10) Patent No.:
`US 6,492,712 B1
`(45) Date of Patent:
`Dec. 10, 2002
`
`(54) HIGH QUALITY OXIDE FOR USE IN
`INTEGRATED CIRCUITS
`
`(75) Inventors: Yuanning Chen, Orlando, FL (US);
`Sundar Srinivasan Chetlur, Singapore
`(SG); Sailesh Mansinh Merchant,
`Orlando, FL (US); Pradip Kumar Roy,
`Orlando, FL (US)
`(73) Assignee: Agere Systems Guardian Corp.,
`Orlando, FL (US)
`
`(*) Notice:
`
`Subject to any disclaimer, the term of this
`patent is extended or adjusted under 35
`U.S.C. 154(b) by 0 days.
`
`(21) Appl. No.: 09/597,077
`(22) Filed:
`Jun. 20, 2000
`Related U.S. Application Data
`(60) Provisional application No. 60/140,909, filed on Jun. 24,
`1999.
`(51) Int. Cl." .............................................. H01L 21/316
`(52) U.S. Cl. ........................................ 257/632; 257/635
`(58) Field of Search ................................. 257/506, 524,
`257/632, 635, 646
`
`(56)
`
`References Cited
`U.S. PATENT DOCUMENTS
`5,707,888 A
`1/1998 Aronowitz
`
`5,739,580 A 4/1998 Aronowitz et al.
`5,885,870 A 3/1999 Maiti et al.
`5,926,741 A 7/1999 Matsuoka et al.
`6,025,280 A * 2/2000 Brady et al. ................ 438/762
`6.210,999 B1 * 4/2001 Gardner et al. ............. 438/762
`
`FOREIGN PATENT DOCUMENTS
`O 323 O71 A2 12/1988 ......... HO1 L/21/316
`2 O56 174. A 3/1981 ......... HO1 L/21/471
`O1204435 A6 * 8/1989
`
`EP
`GB
`JP
`
`OTHER PUBLICATIONS
`
`U.S. patent application Ser. No. 5,622,607, filed Nov. 15,
`1991 and issued on Apr. 22, 1997 to Shunpei Yamazaki et al.
`
`* cited by examiner
`
`Primary Examiner Minh Loan Tran
`Assistant Examiner Thomas Dickey
`(57)
`ABSTRACT
`
`An oxide for use in integrated circuits is Substantially
`stress-free both in the bulk and at the interface between the
`Substrate and the oxide. The interface is planar and has a low
`interface trap density (N). The oxide has a low defect
`density and may have a thickness of less than 1.5 nm or less.
`
`15 Claims, 8 Drawing Sheets
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`
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`26
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`SO
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`22
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 3 of 17 PageID #: 203
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 1 of 8
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`US 6,492,712 B1
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`26 N
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`S 3.
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`22
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`FIC.
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`1A
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 4 of 17 PageID #: 204
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 2 of 8
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`US 6,492,712 B1
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`FIG. 2
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`TEVP
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`TIME
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 5 of 17 PageID #: 205
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 3 of 8
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`US 6,492,712 B1
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`FIG. 3
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`FIC. 4
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`FIC. 5
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`s:
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`22
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`%2-3 -
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`3.
`%
`32
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`22
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 6 of 17 PageID #: 206
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 4 of 8
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`US 6,492,712 B1
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`F.C.
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`6
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 7 of 17 PageID #: 207
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 5 of 8
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`US 6,492,712 B1
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`FIC. 8
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`
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`O
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`O,
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`O
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`100
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`TIME (HRS)
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 8 of 17 PageID #: 208
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 6 of 8
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`US 6,492,712 B1
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`FIC. 9
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`HCA CRITERIA : 15% gm
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`e
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`as a
`d
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`50
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`5.5
`FIELD (MV/cm)
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`6.0
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 9 of 17 PageID #: 209
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 7 of 8
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`US 6,492,712 B1
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`FIC,
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`f f
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`0.00035
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`0.0003
`0.00025
`a 0.0002
`E <s OOOO15
`0.0001
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`000005
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`5,E-04
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`
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`4.E-04
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`3.E-04
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`s
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 10 of 17 PageID #: 210
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`U.S. Patent
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`Dec. 10, 2002
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`Sheet 8 of 8
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`US 6,492,712 B1
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`FIC,
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`13
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`120
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`100
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`80
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`60
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`40
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`20
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`5
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`6
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`7
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`8
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`LEAKAGE (-LOGL)
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`FIC. 14
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`120
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`OO
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`80
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`60
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`40
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`20
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`LEAKAGE (-LOGL)
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`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 11 of 17 PageID #: 211
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`US 6,492,712 B1
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`1
`HIGH QUALITY OXIDE FOR USE IN
`INTEGRATED CIRCUITS
`
`CROSS-REFERENCE TO RELATED
`APPLICATION
`This present application claims priority from Provisional
`Application Serial No. 60/140,909 (filed Jun. 24, 1999).
`FIELD OF THE INVENTION
`The present invention relates to an ultra-thin oxide for use
`as the gate dielectric in metal oxide semiconductor (MOS)
`StructureS.
`
`BACKGROUND OF THE INVENTION
`AS integrated circuit (IC) complexity increases, the size of
`devices within the IC must decrease. To decrease the size of
`a device, the various elements of a device must be reduced
`proportionately. This is known as device Scaling. In one type
`of device, a metal-oxide-semiconductor (MOS) structure,
`device Scaling requires that the oxide layer be made thinner.
`Unfortunately, as conventional oxides are made thinner
`(Scaled), their quality tends to degrade. The degradation in
`oxide quality tends to adversely impact the reliability of a
`device using the oxide.
`In addition to oxide quality, the reliability of the dielectric
`material in a MOS structure may be affected by oxide stress
`and the planarity of the oxide-Substrate interface. Oxide
`StreSS can result from lattice mismatch and growth induced
`StreSS. Lattice mismatch is difficult to overcome and growth
`StreSS has been addressed in a variety of ways with mixed
`results. StreSS in the oxide may lead to defects especially in
`the interfacial region. This may result in mass transport
`paths and leakage current.
`The reliability of a device is characterized by a few
`conventional criteria. For example, in a MOS transistor
`reliability may be characterized in terms of the change in
`conventional device parameters over time (known as device
`parameter drift). Additionally, time-dependent dielectric
`breakdown (TDDB) may be used to characterize reliability
`of the transistor.
`Under operating bias (applied Voltage) and temperature
`conditions, device parameters Such as threshold voltage (V),
`Saturation current (Isa) and transconductance (g) tend to
`drift to unacceptable values. In fact, the drift in device
`parameters during normal operation is thought to be more
`problematic than other known reliability problems, Such as
`dielectric breakdown of the oxide. Accordingly, in Some
`cases, device parameter drift can cause a device to fail well
`before dielectric breakdown occurs.
`In order to address the reliability issues discussed above,
`a variety of approaches have been tried. For example, it is
`known that the best oxides for many IC devices are grown
`rather than deposited oxides. Furthermore, the higher growth
`temperatures may yield a better quality oxide.
`Unfortunately, there are problems associated with fabricat
`ing oxides at high temperatures by conventional techniques.
`For example, in achieving the high temperatures required in
`the high temperature oxide growth Sequence, the overall
`thickness of the oxide grown tends to increase. As a result
`the oxide may be too thick for a reduced dimension device.
`Thus, in the effort to fabricate a better quality oxide, device
`Scaling objectives may be defeated. Moreover, when cooling
`down from the high growth temperatures, the Viscosity of
`the grown oxide increases and undesired growth induced
`StreSS may result. Given these issues, it is customary in the
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`Semiconductor industry to grow oxides at a low tempera
`tures. The drawback to this practice is that by growing oxide
`at lower temperatures, the oxide quality may be compro
`mised. This reduction in quality adversely impacts reliability
`of the oxide for reasons discussed above.
`What is needed, therefore, is a high quality oxide having
`low stress which is sufficiently thin to meet the demands of
`device Scaling in the Semiconductor industry.
`
`SUMMARY OF THE INVENTION
`The present invention relates to an oxide for use in
`integrated circuits. The oxide is disposed over a Substrate
`and the interface between the Substrate and the oxide is
`planar and Substantially StreSS-free. The oxide has a low
`defect density (D) and a low interface trap density (N).
`The oxide of the present invention may have a thickness leSS
`than 4.0 nm; illustratively, 1.5 nm or less.
`
`BRIEF DESCRIPTION OF THE DRAWING
`The invention is best understood from the following
`detailed description when read with the accompanying
`drawing figures. It is emphasized that the various features
`and graphical representations may not necessarily be drawn
`to Scale. In fact, the dimensions of the various features may
`be arbitrarily increased or decreased for clarity of discus
`SO.
`FIG. 1a is a Schematic cross-sectional view of an exem
`plary MOS Structure according to the present invention.
`FIG. 1b is Schematic croSS Sectional view of an exemplary
`MOS transistor according to the present invention.
`FIG. 2 is a graph of temperature VS. time is an exemplary
`fabrication Sequence in accordance with an exemplary
`embodiment of the present invention.
`FIGS. 3-5 are schematic cross sectional views illustrating
`the processing Sequence of forming the oxide layer in
`accordance with an exemplary embodiment of the present
`invention.
`FIG. 6 is a transmission electron microscope (TEM)
`lattice image of a conventional oxide on a Substrate having
`a conductive layer on the oxide.
`FIG. 7 is a transmission electron microscope (TEM)
`lattice image of an oxide layer on a Substrate including a
`conductive layer on the oxide in accordance with an exem
`plary embodiment of the present invention.
`FIG. 8 is a graph of percent degradation of V. (V, drift)
`over time of illustrative oxides of the present invention and
`a conventional oxide.
`FIG. 9 is a graph including plots of time vs. Substrate
`current (I) indicative of hot carrier aging (HCA) for a
`conventional oxide and an oxide layer in accordance with an
`exemplary embodiment of the present invention.
`FIG. 10 is a graph including plots of mean time to failure
`(MTTF) vs. electric field for conventional oxide layers and
`oxide layers in accordance with an exemplary embodiment
`of the present invention.
`FIG. 11 is a comparative graph including plots of
`transconductance (g) VS. gate-Source voltage (V) for
`15x15 um NMOSFETs incorporating conventional gate
`oxide layers and those incorporating gate oxide layers in
`accordance with an exemplary embodiment of the present
`invention.
`FIG. 12 is a comparative graph including plots of drain
`currents (I) vs. drain voltage (V) for a 15x15 um NMOS
`FETs incorporating conventional gate oxide layerS and those
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`3
`incorporating gate oxide layers in accordance with an exem
`plary embodiment of the present invention.
`FIG. 13 is a comparative graph including plots of cumu
`lative probability vs. leakage for 15x15 m FETS in a n-type
`tub including conventional gate oxide layerS and gate oxide
`layers in accordance with an exemplary embodiment of the
`present invention.
`FIG. 14 is a comparative graph including plots of cumu
`lative probability vs. leakage for 15x15 um FETS in a
`p-type tub including conventional gate oxide layerS and gate
`oxide layers in accordance with an exemplary embodiment
`of the present invention.
`DETAILED DESCRIPTION
`The present invention will now be described more fully
`with reference to the accompanying drawing figures, in
`which exemplary embodiments of the present invention are
`shown. Referring to FIG. 1a, an oxide layer 30 in accor
`dance with an exemplary embodiment of the present inven
`tion is first described. Illustratively, the oxide layer 30 is
`incorporated into an integrated circuit (not shown). The
`oxide layer 30 is disposed over a substrate 22, and includes
`a first oxide portion 31 and a second oxide portion 32. The
`second oxide portion 32 forms an interface 34 with the
`substrate 22. The substrate 22 is illustratively silicon; it may
`be monocrystalline or polycrystalline Silicon. Most gener
`ally it is oxidizable silicon.
`Illustratively, the oxide layer 30 has a thickness of
`approximately 40 A or less. It is anticipated that the thick
`ness of the oxide layer 30 may be 15 A-20 A; and may be
`even less than 15 A. Moreover, the oxide layer may have a
`layer of material 33 disposed between it and a conductive
`layer 26. Layer 33 may be a high-k material, including but
`not limited to tantalum pentoxide, barium-Strontium titanate,
`and Silicate dielectric materials. Additionally, other materi
`als may be disposed between the conductive layer 26 and the
`oxide layer 30 to achieve a variety of results as would be
`appreciated by the artisan of ordinary skill.
`A characteristic of the present invention is that the inter
`face 34 between the second oxide portion 32 and the
`Substrate 22 is Substantially planar. This planarity is gener
`ally measured in terms of Surface roughness. In the oxide of
`the present invention the interface has a Surface roughness of
`approximately 3 A or less. Moreover, the interface 34
`between the Substrate 22 and the second oxide portion 32 is
`substantially stress-free, having 0 to 2x10' dynes/cm of
`compression. This results in a defect density (D) on the
`order of 0.1 defects/cm or less. Finally, the second oxide
`portion 32 is believed to be a more dense layer of oxide,
`when compared to conventional oxides. As a result of the
`dense and Substantially StreSS free characteristics of the
`oxide, the interface trap density (N) of the oxide of the
`present invention is on the order of 5x10"/cm to 3 x10/
`cm or less.
`The resultant ultra-thin oxide having improved planarity,
`being Substantially StreSS free and being more dense has
`clear advantages over conventional oxides. These advan
`tages include improvements in both reliability and perfor
`mance in devices incorporating the oxide of the present
`invention. To this end, deleterious effects of device param
`eter drift and time dependent dielectric breakdown (TDDB)
`are reduced by virtue of the present invention. Moreover,
`device performance may be improved through reduced
`leakage current and increased mobility, for example. These
`characteristics of the oxide of the present invention and the
`improvements in reliability and performance are discussed
`more fully herein.
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`The exemplary embodiment of FIG. 1a is generally a
`MOS structure. Clearly a variety of devices and elements
`may incorporate this structure. These include, but are not
`limited to a MOS transistor (described below) and a MOS
`capacitor, a common element in integrated circuits. Still
`other devices and elements may incorporate the oxide of the
`present invention, as would be readily apparent to one
`having ordinary skill in the art to which the present invention
`relates.
`In the exemplary embodiment shown in FIG. 1b, the
`oxide layer 30 is incorporated into a MOS transistor 21. The
`MOS transistor includes a source 23 and a drain 24, sepa
`rated by a channel 25. The transistor may also include lightly
`doped Source and drain regions 27 and 28, respectively. The
`Source, drain and channel may be fabricated by a variety of
`conventional techniques to form a variety of transistor
`structures including but not limited to PMOS, NMOS
`complementary MOS (CMOS) and laterally diffused MOS
`(LDMOS) devices.
`Turning to FIG. 2, an exemplary Sequence for fabricating
`the oxide layer 30 by fast thermal processing (FTP) is
`shown. (CrOSS Sectional views of this exemplary growth
`Sequence and the resulting oxide Structure are shown in
`FIGS. 3-5). Segment 20 indicates a wafer boat push step at
`an initial temperature of approximately 300 C-700 C.,
`with nitrogen flow of 8.0 L/min and 0.02 to 1% ambient
`oxygen concentration. These parameters are chosen to mini
`mize the growth of native oxide, which can degrade oxide
`quality as well as consume the allowed oxide thickness
`determined by Scaling parameters (referred to as oxide
`thickness budget or Scaling budget). Additionally, a load
`lock System or a hydrogen bake, well known to one of
`ordinary skill in the art, can be used to impede the growth
`of this undesirable low-temperature oxide.
`Segment 21 is a rapid upward temperature increase at
`approximately 50–125° C. per minute to about 750 C-850
`C. This Step is carried out at a very low oxygen ambient
`concentration (on the order of 0.05% to 5%) and a high
`nitrogen ambient. One aspect of the present embodiment
`relates to the Step of upwardly ramping the temperature at a
`relatively high rate (Segment 21) to minimize the thickness
`of the oxide formed in this segment (known as the ramp
`oxide). This helps control the overall thickness of the oxide
`30. Thus, through this step, the desired higher growth
`temperatures (segments 23 and 26) may be attained without
`Sacrificing the oxide thickness budget. Moreover, this rapid
`rise in temperature at low ambient oxygen concentrations
`retards the growth of lower temperature oxide, which may
`be of inferior quality, as discussed above.
`Segment 22 is a more gradual increase in temperature.
`Segment 22 proceeds at approximately 10–25 C. per
`minute. In the exemplary embodiment the temperature
`reached at the end of Segment 22 is in the range of approxi
`mately 800° C. to 900 C. The same oxygen and nitrogen
`flowS/concentrations used in Segment 21 are maintained in
`Segment 22. This control of the ramp up in temperature in
`Segment 22 is also useful as it helps to prevent overshooting
`the growth temperature of Segment 23. Finally, the low
`concentration of oxygen in Segment 22 Selectively retards
`the growth of oxide during the temperature increase to a
`higher growth temperature. Again this helps to preserve the
`oxide thickness budget.
`Segment 23 is a low temperature oxide (LTO) growth
`Step. In this Step, the ambient oxygen concentration is about
`0.1% to about 10% while the ambient nitrogen concentration
`is 90–99.9%. Dichloroethyline may be added at 0-0.5% for
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`a time that is dependent upon the desired thickness as would
`be appreciated by one of ordinary skill in the art. At the end
`of Segment 23, an anneal in pure nitrogen may be carried
`out. In the illustrative Sequence of FIG. 2, during Segments
`20–22 an oxide is grown having a thickness in the range of
`5–10 A. Segment 23 results in the growth of approximately
`2.5–10 A of oxide. Upon completion of Segment 23, the
`growth of the first oxide portion 31 (in FIG. 4) is completed.
`Illustratively, this first oxide portion 31 is grown at a
`temperature lower than the Viscoelastic temperature of sili
`con dioxide (T), which is approximately 925 C. The first
`oxide portion 31 may comprise 25-98% of the total thick
`ness of the oxide layer 30. In an exemplary embodiment in
`which the oxide layer 30 has a thickness of 30 A or less, the
`first oxide portion 31 has a thickness of approximately
`7.5–20 A. As discussed more fully herein, applicants theo
`rize that the first oxide portion 31 acts as a Sink for StreSS
`relaxation that occurs during the growth of Second oxide
`portion 32 under first oxide portion 31.
`Segment 24 is the first Segment in the temperature
`increase to a temperature above the Viscoelastic temperature
`of Silicon dioxide. This ramp up in temperature occurs
`relatively slowly, at a rate of approximately 5-15 C. per
`minute and in a nearly pure nitrogen ambient (the ambient
`concentration of oxygen in this Segment is illustratively
`0%-5%). The temperature reached at the end of segment 24
`is approximately 50° C. below the high temperature oxide
`(HTO) growth temperature of segment 26. Segment 25 is a
`modulated heating Segment in which the temperature is
`increased at a rate of approximately 5-10 C. per minute to
`a temperature above the Viscoelastic temperature. In the
`illustrative embodiment the HTO growth temperature is in
`the range of 925-1100° C. The same flows/concentration of
`oxygen and nitrogen of Segment 24 are used in Segment 25.
`At the end of segment 25, the HTO growth temperature is
`reached.
`Segments 24 and 25 are useful steps in the of the
`exemplary embodiment of the present invention. AS was the
`case in the temperature ramp-up to segment 23 (the LTO
`growth segment) the careful ramp-up of temperature in
`Segments 24 and 25 prevents overshooting the desired
`growth temperature, in this case the HTO growth tempera
`ture of the present invention. The rate of temperature
`increase at the illustrated low ambient OXygen concentration
`is useful in retarding oxide growth thereby preserving the
`oxide thickneSS budget. Finally, applicants believe that the
`careful heating rate in a low oxygen ambient in Segments 24
`and 25 reduces growth StreSS, and consequently a reduces
`the occurrence of oxide growth defects (e.g. slip dislocations
`and Stacking faults).
`Segment 26 is the HTO growth step where the growth
`temperature is illustratively above the Viscoelastic tempera
`ture of Silicon dioxide. The temperature achieved at the end
`of Segment 25 is maintained in the growth Step in Segment
`26 in a 0 to 25% oxygen ambient for approximately 2 to 20
`minutes so that an additional 2-12A of oxide may be grown
`at high temperature. The Second portion may comprise on
`the order of 2-75% of the total thickness of the oxide layer
`30. The final portion of segment 26 may include an anneal
`in pure nitrogen. Applicants believe (again without wishing
`to bound) that the high temperature growth above the
`viscoelastic temperature (approximately 925 C.) results in
`the growth of an oxide (Second oxide portion 32) having
`certain properties. For example, it is believed that the Second
`oxide portion 32 is more amorphous, and thereby has little,
`if any, crystalline Structure and short range order. This
`results in a denser oxide. To this end, the SiO4 tetrahedron
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`structure connected by O-Si-O chain, (characteristic of
`Silicon dioxide) is more random than in conventional oxides.
`The random nature of the molecular structure of the Second
`oxide portion 32 results in a more densely packed oxide.
`Accordingly, as will be appreciated through the discussion
`herein, the second oxide portion 32 is believed to have
`shorter Si-O bond length and greater Si-O bond strength
`when compared to conventionally grown oxide.
`Segment 27 of the exemplary embodiment of FIG. 2 is a
`cooling Segment also referred to as a modulated cooling
`Segment. A temperature ramp down is carried out at a rate of
`approximately 2–5 C. per minute to a temperature at the
`end of segment 27 which is below the viscoelastic tempera
`ture. For example, the temperature reached at the end of
`segment 27 is in the range of 900-800° C. Segment 27 is
`carried out in a nearly pure nitrogen ambient, which is inert.
`During the cooling of a grown oxide to below the Viscoelas
`tic temperature, StreSS may result in the oxide, particularly at
`the Substrate-oxide interface. As a result of this StreSS,
`defects Such as Slip dislocations and oxidation induced
`Stacking faults may be formed at energetically favored Sites
`Such as heterogenities and asperities. These defects may be
`Viewed as routes for diffusional mass transport and leakage
`current paths which can have a deleterious impact on
`reliability and device performance. The modulated cooling
`Segment, and the StreSS absorbing or StreSS Sink character
`istics of the first oxide portion 31 (particularly during the
`modulated cooling segment) results in a Substantially stress
`free oxide-substrate interface. Moreover, the defect density
`is reduced. Finally, Segment 28 represents a further ramp
`down at a faster rate on the order of approximately 35-65
`C. per minute again in an inert ambient Such as pure
`nitrogen. Segment 29 is the boat pull at about 500 C. in a
`pure nitrogen ambient.
`FIGS. 3-5 show the cross sectional view of the steps of
`forming the oxide 30. The substrate 22 is generally
`oxidizable, illustratively monocrystalline or polycrystalline
`Silicon, or Silicon islands in Silicon on insulator (SOI)
`substrates. The first oxide portion 31 may be considered the
`low temperature oxide (LTO) portion, having been formed
`primarily below approximately 925 C. In addition to pro
`Viding a StreSS Sink during the formation of the Second oxide
`portion 32 the first oxide portion 31 enables oxide growth
`thereunder. As such, first oxide portion 31 must allow the
`diffusion of oxygen there through So that oxidation of the
`Substrate 22 can occur, resulting in the Second oxide portion
`32. In the illustrative embodiment, the first portion is silicon
`dioxide. However, other materials may be used in this
`capacity as well. Alternative materials include but are not
`limited to a lightly nitrided (for example 0.2 to 3% nitrogen
`by weight) silicon dioxide layer So that boron penetration is
`prevented, which is beneficial in the prevention of poly
`depletion. Moreover, the first oxide portion 31 may be steam
`oxide or a grown-deposited composite oxide layer. The
`Second oxide portion 32 may be considered the high tem
`perature oxide (HTO) portion grown at a temperature above
`the viscoelastic temperature of 925 C. For purposes of
`illustration, the high temperature growth of the Second
`portion 32 is 925 C-1 100° C.
`Characteristics of the oxide layer 30 of the present inven
`tion include improved interfacial planarity and a reduction in
`the stress both in the bulk of the oxide and at the interface
`between the oxide and the substrate. This becomes readily
`apparent from a comparison of the FIGS. 6 and 7.
`FIG. 6 is a TEM lattice image of a MOS structure
`incorporating conventional oxide; FIG. 7 is a TEM lattice
`image a MOS structure incorporating the exemplary oxide
`
`

`

`Case 2:20-cv-00048-JRG Document 1-9 Filed 02/21/20 Page 14 of 17 PageID #: 214
`
`US 6,492,712 B1
`
`15
`
`8
`36 A (plot 81) and 32 A (plot 82) is compared to a
`conventional oxide having a thickness of 33 A (plot 83). As
`is clear from FIG. 8, bias temperature (BT) drift is signifi
`cantly lower in devices using the oxide of the present
`invention.
`Another phenomenon that can adversely impact the reli
`ability of a device is hot carrier aging (HCA). In Sub-micron
`gate Structures, hot carrier effects result from a increased
`lateral electric field in the reduced length channel. This
`causes inversion-layer charges to be accelerated (or heated)
`to an extent that they may cause a number of harmful device
`phenomena, commonly referred to as hot carrier effects. An
`important hot carrier effect from the standpoint of reliability
`in devices is the damage inflicted on the gate oxide and/or
`the silicon-silicon dioxide interface by hot carriers. Hot
`carrier aging is believed to be due to interface trap genera
`tion or the breaking of passivating dangling bonds. To this
`end, dangling bonds in the Silicon-Silicon dioxide interface
`are conventionally passivated in a hydrogen ambient,
`thereby reducing the number of interface traps. While this
`passivation technique has met with Some Success in con
`ventional oxides, hot carriers can readily break Silicon
`hydrogen bonds, thereby re-establishing the previously pas
`Sivated interface traps. The traps in the interface act as
`Scattering centers, thereby reducing the mobility of carriers
`within the channel. AS is known, the drive current, I, (or
`Saturation current, I), and the transconductance g are
`directly proportional to the mobility of the carriers in the
`channel. Accordingly, as the Scattering centers become more
`abundant due to hot carrier effects, the mobility of carriers
`in the channel is reduced, and the drive current and transcon
`ductance are reduced. Thus, the number of interface traps
`can cause the device to degrade (age) due to drift in device
`parameterS Such as drive current and transconductance. This
`degradation has a deleterious impact on device reliability.
`The oxide of the present invention has a reduced inci
`dence of dangling Silicon bonds, and thereby a reduced
`number of interface traps. Applicants theorize that this is a
`result of a more complete oxidation process and because the
`interface is Substantially StreSS-free and planar. Moreover,
`Since there are fewer interface traps in the oxide of the
`present invention, there are fewer traps to be passivated with
`hydrogen. It is anticipated that there will be less device drift
`due to hydrogen release in devices which incorporate the
`oxide of the present invention.
`Measured by Standard technique, the interface trap den
`sity (N) of the oxide of the present invention is on the order
`of 3x10/cm' to 5x10'/cm’ or less. The resulting improve
`ment in hot carrier aging can be seen clearly in the graphical
`representation of FIG. 9. The hot carrier aging criteria by
`convention is a 15% change in transconductance. The plot
`labeled 90 is for a device incorporating a 32 A oxide layer
`fabricated in accordance with the present invention. The plot
`labeled 91 is for a device incorporating for a conventional
`oxide of the same thickness. For example, the Substrate
`current limit of 3 u/um is achieved at 120 hours in a
`conventional oxide in a MOSFET, in an exemplary oxide of
`the present invention this is limit achieved at 400 hours. As
`will be readily appreciated of those of ordinary skill in the
`art, hot carrier aging is improved by a factor of 3-10 by the
`oxide of the present invention when compared to conven
`tional oxides.
`The oxide of the present invention also results in an
`improvement of the time dependent dielectric breakdown
`(TDDB), another measure of reliability of the MOS device.
`This improvement in TDDB is believed to be a direct result
`of the StreSS free and high quality Silicon-Silicon dioxide
`
`7
`of the present invention. FIG. 6 shows a substrate 62, a
`conventional oxide layer 60 and a conductive layer 66. In the
`image of FIG. 6, there is a stress band 63 (dark contrast)
`indicating the existence of a strain field between the oxide 60
`and the Substrate 62. In addition, the interface between the
`oxide 60 and the substrate 62 is relatively rough (i.e. not
`planar). Conventional oxides exhibit a surface roughness on
`the order of 5 A or greater. Among other drawbacks, this
`degree of roughness can result in carrier Scattering in the
`channel of an exemplary MOS transistor, resulting in
`reduced carrier mobility.
`In contrast to the conventional oxide in FIG. 6, the
`interface between the graded grown oxide 30 and the
`Substrate 22 in the exemplary embodiment of the present
`invention shown in FIG. 7 shows no dark contrast in the
`TEM image. Therefore, there is no noticeable stress band.
`Instead, the interface between the graded grown oxide 30
`and the Substrate 22 in the illustrative embodiment is Sub
`stantially stress free. Moreover, the interface is substantially
`planar without any observable breakage in the Si (111) lines
`near the interface. Using Standard StreSS measurement tech
`niques Such as X-ray micro-diffraction techniques, the sili
`con (400) Bragg peak profile indicates 0 to 2x10' dynes/cm
`of compression by Warren-AVerbach analysis. In contrast
`conventional oxides exhibit 9x10' to 1x10' dynes/cm of
`25
`tension. Furthermore, although not discernable in the TEM
`of FIG. 7, the bulk oxide is substantially stress free having
`0-2x10' dynes/cm of compression measured by similar
`technique. Finally, the interface between the oxide 30 and
`the Substrate 22 is Substantially planar having a planarity
`that is not detectable within the resolution of conventional
`TEM imaging devices (approximately 3 A).
`As alluded to above, by virtue of the substantially stress
`free and planar Si-SiO interface and the denser Second
`oxide portion 32 formed by the present invention oxide of
`the present invention, there are improvements in the reli
`ability of devices employing the oxide of the present inven
`tion. The device parameter drift during normal operation is
`often more Significant than oxide breakdown when evalu
`ating the reliability device employing the thin gate oxide.
`Device parameter drift can cause a device to fail the required
`parameter Specifications long before an oxide breakdown
`event occurs. Drift in devices is dominated by two mecha
`nisms. In a p-MOS device, bias-temperature (BT) drift is the
`dominant factor, while in an n-MO