Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 1 of 11 PageID #: 211
`Case 4:20-cv-00991—ALM Document 1-8 Filed 12/31/20 Page 1 of 11 PageID #: 211
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`EXHIBIT H
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`EXHIBIT H
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 2 of 11 PageID #: 212
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`Analysis of Infringement of U.S. Patent No. 6,660,651 by Huawei Device USA Inc., Huawei Device Co., Ltd., and HiSilicon Technologies Co.,
`Ltd. (Based on Public Information Only)
`
`Plaintiff Ocean Semiconductor LLC (“Ocean Semiconductor”), provides this preliminary and exemplary infringement analysis with respect to
`
`infringement of U.S. Patent No. 6,660,651, entitled “ADJUSTABLE WAFER STAGE, AND A METHOD AND SYSTEM FOR PERFORMING
`PROCESS OPERATIONS USING SAME” (the “’651 patent”) by Huawei Device USA Inc., Huawei Device Co., Ltd., and HiSilicon Technologies
`Co., Ltd. (“Huawei”). The following chart illustrates an exemplary analysis regarding infringement by Defendant Huawei’s semiconductor products,
`systems, devices, components, and integrated circuits, and products containing such circuits, fabricated or manufactured using ASML’s
`semiconductor fabrication or manufacturing equipment and/or platforms (e.g., ASML’s TWINSCAN system). Such products include, without
`limitation, SoC chipsets and solutions (e.g., Hi3559A V100, Hi3519A V100, Hi3516D V300, Hi3556A V100, Hi3559 V200, Hi3559A V100,
`Hi3559C V100, Hi3559 V100, Hi3716M V430, Hi3716M V430, Hi3798C V200, Hi3798M V200H, Hi3798M V300, Hi3798M V310, Hi3796M
`V200, Hi3798M V200, Hi3796M V100, Hi3798M V100, Hi3716M V420, Hi3716M V410, and Hi3751 V553), processors (e.g., Hi3536, Hi3536C,
`Hi3536D V100, Hi3531D V100, Hi3521D V100, Hi3520D V400, Hi3520D V300, and Hi3520D V200), TV solutions (e.g., Hi3731 V201, Hi3731
`V101, Hi3751 V811, HI3751 V810, Hi3751 V551, Hi3751 V730, Hi3751 V620, Hi3751 V510, Hi3751 V310, Hi3751 V320, and Hi3751 V600),
`Kirin solutions (e.g., Kirin 9000/E, Kirin 1020, Kirin 990, Kirin 980, Kirin 970, Kirin 960, Kirin 950, Kirin 930, Kirin 920, Kirin 910, and Kirin
`710); Ascend solutions (e.g., Ascend 310 and Ascend 910); Kunpeng solutions (e.g., Kunpeng 920); and Balong solutions (e.g., Balong 5000, Balong
`5G01, Balong 765, Balong 750, Balong 720, Balong 710, and Balong 700), systems, products, or devices containing these solutions, and similar
`systems, products, devices, and integrated circuits (“’651 Infringing Instrumentalities”).
`
`The analysis set forth below is based only upon information from publicly available resources regarding the ’651 Infringing Instrumentalities,
`
`as Huawei has not yet provided any non-public information.
`
`Unless otherwise noted, Ocean Semiconductor contends that Huawei directly infringes the ’651 patent in violation of 35 U.S.C. § 271(g) by
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`using, selling, and/or offering to sell in the United States, and/or importing into the United States, the ’651 Infringing Instrumentalities. The
`following exemplary analysis demonstrates that infringement. Unless otherwise noted, Ocean Semiconductor further contends that the evidence
`below supports a finding of indirect infringement under 35 U.S.C. § 271(b) in conjunction with other evidence of liability.
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`Unless otherwise noted, Ocean Semiconductor believes and contends that each element of each claim asserted herein is literally met through
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`Huawei’s provision or importation of the ’651 Infringing Instrumentalities. However, to the extent that Huawei attempts to allege that any asserted
`claim element is not literally met, Ocean Semiconductor believes and contends that such elements are met under the doctrine of equivalents. More
`specifically, in its investigation and analysis of the ’651 Infringing Instrumentalities, Ocean Semiconductor did not identify any substantial
`differences between the elements of the patent claims and the corresponding features of the ’651 Infringing Instrumentalities, as set forth herein. In
`each instance, the identified feature of the ’651 Infringing Instrumentalities performs at least substantially the same function in substantially the same
`way to achieve substantially the same result as the corresponding claim element.
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 3 of 11 PageID #: 213
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`Ocean Semiconductor notes that the present claim chart and analysis are necessarily preliminary in that Ocean Semiconductor has not
`obtained substantial discovery from Huawei nor has Huawei disclosed any detailed analysis for its non-infringement position, if any. Further, Ocean
`Semiconductor does not have the benefit of claim construction or expert discovery. Ocean Semiconductor reserves the right to supplement and/or
`amend the positions taken in this preliminary and exemplary infringement analysis, including with respect to literal infringement and infringement
`under the doctrine of equivalents, if and when warranted by further information obtained by Ocean Semiconductor, including but not limited to
`information adduced through information exchanges between the parties, fact discovery, claim construction, expert discovery, and/or further analysis.
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 4 of 11 PageID #: 214
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`Infringement by the ’651 Accused Instrumentalities
`ASML’s TWINSCAN system provides a process chamber comprised of a wafer stage, the wafer stage having a
`surface that is adjustable.
`
`For example, the TWINSCAN system performs the method of providing a process chamber:
`
`
`USP No. 6,660,651
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`19. A method,
`comprising: providing a
`process chamber
`comprised of a wafer
`stage, said wafer stage
`having a surface that is
`adjustable;
`
`
`
`See ASML DUV Lithography Systems, available at https://www.asml.com/en/products/duv-lithography-
`systems/twinscan-nxt1980di (last visited Apr. 30 2019).
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`The process chamber can be used for wafer exposure during lithography:
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 5 of 11 PageID #: 215
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`
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`See Perspective on Stage Dynamics and Control at 3.
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`The process chamber includes an adjustable wafer stage having a surface that is adjustable:
`
`“In Figure 4, the table holding the wafer is called the mirror block because of the mirroring side surfaces, which
`allow interferometric position measurement (IFM).”
`
`See Position Control at 31.
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`For example, the adjustable wafer stage or mirror block of the TWINSCAN system is shown below:
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 6 of 11 PageID #: 216
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`adjusting said surface of
`said wafer stage by
`actuating at least one of
`a plurality of pneumatic
`cylinders that are
`operatively coupled to
`said wafer stage to
`accomplish at least one
`of raising, lowering and
`varying a tilt of said
`surface of said wafer
`stage;
`
`
`
`
`
`See Applications Products and Business Opportunity at 6.
`
`ASML’s TWINSCAN system adjusts the surface of the wafer stage by actuating at least one of a plurality of
`pneumatic cylinders that are operatively coupled to said wafer stage to accomplish at least one of raising, lowering
`and varying a tilt of said surface of said wafer stage.
`
`For example, the TWINSCAN system adjusts the surface of the wafer stage by raising, lower, or tilting via wafer
`leveling using vertical actuators (e.g., in the “z direction”):
`
`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
`
`See Position Control at 41; see also id. at 38 (“For wafer leveling, the actuators drive the mirror block with respect
`to the air foot, and hence vertical reaction forces can directly enter the silent, vibration-free, metro-frame world.
`Leveling now needs to be performed during scanning, making use of the wafer-height measurement by the level
`sensor.”).
`
`As another example, the TWINSCAN system actuates one of the six Lorentz actuators that are mounted between
`the air foot and the wafer stage to accomplish at least one of raising, lowering and varying a tilt of the surface of
`the wafer stage:
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 7 of 11 PageID #: 217
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`“Vertical actuators, which are mounted between the air foot and mirror block, allow the mirror block to be moved
`in z direction, as well as in rotational directions around the x and y axes, called x and Ψ, respectively.”
`
`See Position Control at 41.
`
`Generally, the wafer stage is equipped with DOF Lorentz actuators (e.g., three DOF actuators for the horizontal
`directions and three DOF actuators for the vertical directions):
`
`“The table also had vertical movement directions for the purpose of focusing the wafer in the image plane of the
`lens, requiring a measurement of the distance of the wafer to the lens by means of a level sensor system. The
`horizontal stage position was measured by an interferometer system. The stage was guided by means of
`mechanical bearings ‘rolling’ over the motor beams. With regard to controlling the stage, the horizontal
`controllers (3-DOF) acted independently from the vertical directions (also 3-DOF).”
`
`See Perspective on Stage Dynamics and Control at 1.
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`As an example, for the x and y direction, the wafer table is adjusted by three Lorentz actuators such that the stage
`floats over a granite stone by means of an air bearing and the Lorentz actuators are connected to this granite stone:
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 8 of 11 PageID #: 218
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`
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`See Position Control at 31.
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`In total, the TWINSCAN includes 6-DOF Lorentz actuators and 6-DOF stage control, in addition to offline
`leveling:
`
`“In TWINSCANTM, a further perfection in the basic design was made by using balance masses, full 6-DOF
`Lorentz actuators and 6-DOF stage control, in addition to off-line levelling.”
`
`See Perspective on Stage Dynamics and Control at 3.
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`As another example, the vertical directions of the wafer stage can be achieved using Lorentz actuators:
`
`“To avoid vibrations entering the mirror block, a Lorentz actuator is now also used for vertical directions, providing
`isolation in these directions as well. Because the required vertical range is smaller than 1 mm, no separate long-stroke
`motor is required. A 6DOF Lorentz-actuated block is the result”
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 9 of 11 PageID #: 219
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`See Position Control at 40.
`
` A
`
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`
` diagram showing the vertical connection that facilitates the vertical movement of the wafer stage is shown below:
`
`
`
`
`See Position Control at 41 (annotated).
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`In one example, the wafer stage rotates around the center of the lens above it in the vertical directions using the
`actuators:
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`“The stage now rotates around the lens center instead of its center of mass. Especially in the vertical directions, the
`applicable rotations may show a high acceleration, depending on the vertical topology of the wafer surface.”
`
`See Position Control at 42.
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 10 of 11 PageID #: 220
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`positioning a wafer on
`said wafer stage; and
`
`
`performing a process
`operation on said wafer
`positioned on said wafer
`stage.
`
`The wafer stage can also be tilted to help keep the wafer in focus:
`
`“The reason for this lies in the scanning levelling: when the stage has to tilt around a horizontal axis to keep the wafer
`in focus, the stage tends to rotate around its center of mass, introducing a horizontal shift on wafer level.”
`
`See Perspective on Stage Dynamics and Control at 2.
`
`ASML’s TWINSCAN system positions a wafer on the wafer stage.
`
`For example, the TWINSCAN system positions the wafer on the wafer stage:
`
`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
`
`See Position Control at 35.
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`The wafer is also loaded onto the wafer stage so that exposure can start:
`
`“At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect
`to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned to the
`reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
`
`See Position Control at 40.
`
`
`ASML’s TWINSCAN system performs a process operation on the wafer position on the wafer stage.
`
`For example, the TWINSCAN system performs stepper imaging or double patterning as part of the step-and-scan
`in exposing a wafer:
`
`“After stepping the wafer to a new position, the wafer stage is allowed to wait until its position has settled such
`that the remaining error is sufficiently low before switching on the illuminating light. The MA and MSD after the
`step motion indicate the usability of the system for imaging.”
`
`See Position Control at 35.
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`Case 4:20-cv-00991-ALM Document 1-8 Filed 12/31/20 Page 11 of 11 PageID #: 221
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`Once the wafer is loaded, and its surface is mapped in horizontal and vertical planes with respect to the stage itself,
`the stage positioned under the projection lens is aligned to the reticle by means of a through-the-lens optical system.
`With the wafer surface position known with respect to the stage and the stage position known with respect to the
`reticle, exposure can start:
`
`“Stage position measurement is now performed in all degrees of freedom by interferometers, with reference beams
`directed at the projection lens. This method provides a direct relative measurement of the position with respect to
`the lens. At the second stage, the wafer is loaded, and its surface is mapped in horizontal and vertical planes with
`respect to the stage itself. After the stage swap, the stage that is now positioned under the projection lens is aligned
`to the reticle in 6DOF by means of a through-the-lens optical system. With the wafer surface position known with
`respect to the stage and the stage position known with respect to the reticle, exposure can start.”
`
`See Position Control at 40.
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`10
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