Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 1 of 165
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 1 of 165
`
`EXHIBIT 5
`EXHIBIT 5
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 1 of 165
`
`EXHIBIT 5
`EXHIBIT 5
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 2 of 165
`
`
`
`
`U.S. Patent No. 9,858,218
`SK hynix HMA84GL7AMR4N-UHTE
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 3 of 165
`
`1. A memory module
`operable with a memory
`controller of a host system,
`comprising:
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`The SK hynix Products are memory modules operable with a memory controller of a host system.
`
`For example, the SK hynix Products are DDR4 load reduced dual in-line memory modules (“LRDIMM”).
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`
`
`
`
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet, at 1.
`
`
`Page 1 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 4 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 3 (annotation added).
`
`
`JEDEC LRDIMM Specification at 1.
`
`
`Page 2 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 5 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`JEDEC LRDIMM Specification at 5 (annotation added).
`
`The SK hynix HMA84GL7AMR4N-UHTE is manufactured according to JEDEC specifications:
`
`See SKH DDR4 Module Label Info at 3.
`
`
`See SKH DDR4 Module Label Info at 3.
`
`
`Page 3 of 163
`
`
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 6 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`
`
`
`See JEDEC Annex D - Raw Card D at 1.
`
`The SK hynix Products are intended for use as main memory in systems such as servers and workstations.
`
`
`JEDEC LRDIMM Specification at 5 (annotation added).
`
`
`Page 4 of 163
`
`
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 7 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 3 (annotations added).
`
`The SK hynix Products are operable with a memory controller of a host system. For example, the SK hynix Products
`include a printed circuit board (PCB) for communicating signals between (e.g., to/from) the memory module and the
`memory controller of a host system.
`
`
`JEDEC LRDIMM Specification at 17.
`
`For example, the SK hynix Products contain contacts for connecting to a memory controller of a computer system.
`
`
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE)
`
`Page 5 of 163
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 8 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 65 (annotations added).
`
`For example, the SK hynix include a JEDEC RCD01 compliant register clock driver (“RCD”) that is operable with a
`memory controller of a host system.
`
`
`
`
`See, e.g., JEDEC LRDIMM Specification at 12 (annotation added).
`
`
`Page 6 of 163
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 9 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 65 (annotations added).
`
`Specifically, the SK hynix Products contain a IDT 4RCD0124KC0 RCD.
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`Page 7 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 10 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`The IDT 4RCD0124KC0 RCD is JEDEC Compliant.
`
`
`See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.
`
`
`
`
`
`
`IDT Leader in Server Memory Chipsets at 1.
`
`The SK hynix Products further comply with the JEDEC SDRAM Standard, JESD79-4.
`
`
`
`
`Page 8 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 11 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`JEDEC DDR4 SDRAM Specification at 1 (annotations added).
`See also SKH DDR4 Device Operation at 1.
`
`The RCD is operatively coupled to the memory controller of the host system.
`
`
`
`
`Page 9 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 12 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"1. A memory module operable with a memory controller of a host system, comprising:"
`
`JEDEC LRDIMM Specification at 17 (annotations added).
`
`
`
`
`
`Page 10 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 13 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`The SK hynix Products include a printed circuit board having edge connections that fit into a corresponding slot of the
`host system so as to be in electrical communication with the memory controller, the edge connections including first edge
`connections, second edge connections, and an error edge connection in addition to the first edge connections and the
`second edge connections.
`
`The SK hynix Products include a printed circuit board (PCB) having edge connections that fit into a corresponding slot of
`the host system so as to be in electrical communication with the memory controller.
`
`For example, the PCB of the SK hynix Products is configured to fit into a corresponding slot of the host system.
`
`
`a printed circuit board
`having edge connections that
`fit into a corresponding slot
`of the host system so as to be
`in electrical communication
`with the memory controller,
`the edge connections
`including first edge
`connections, second edge
`connections, and an error
`edge connection in addition
`to the first edge connections
`and the second edge
`connections;
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 3 (annotation added).
`
`
`
`
`
`
`JEDEC LRDIMM Specification at 5 (annotation added).
`
`For example, as illustrated in the figures below, the SK hynix Products include a printed circuit board (PCB) having edge
`connections for communicating signals between (e.g., to/from) the memory module and the memory controller of the host
`system, e.g., electrical communication between the memory module and the memory controller.
`
`
`Page 11 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 14 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`JEDEC LRDIMM Specification at 17.
`
`
`JEDEC LRDIMM Specification at 30 (annotations added).
`
`Page 12 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 15 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`
`For example, the SK hynix Products contain contacts (e.g., edge connections) for connecting to a memory controller of a
`computer system.
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE)
`
`
`
`
`Page 13 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 16 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 65 (annotations added).
`
`The edge connections of the SK hynix Products include a first edge connections, second edge connections, and an error
`edge connection in addition to the first edge connections and the second edge connections.
`
`
`
`
`Page 14 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 17 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`See, e.g. JEDEC LRDIMM Specification at 10 (showing, for example, WE_n, A0, DQ4).
`
`
`See, e.g. JEDEC LRDIMM Specification at 11 (showing, for example, ALERT_n).
`
`
`Page 15 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 18 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 10 (showing separate pin connections for data, address,
`control, and ALERT_n).
`
`For example, the SK hynix Products include first edge connections for communicating data signals between the memory
`module and the memory controller of the host system. For example, the SK hynix Products include the following
`input/output pins:
`
`Page 16 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 19 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`
`
`
`
`
`
`JEDEC LRDIMM Specification at 7-9 (annotations added).
`See also SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 5, 7.
`
`
`Page 17 of 163
`
`
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 20 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`The DQ and DQS signals are used to communicate data signals between the memory module and the memory controller
`of the host system.
`
`
`
`
`JEDEC LRDIMM Specification at 17 (annotations added).
`
`
`Page 18 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 21 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`JEDEC DDR4 SDRAM Specification at 17 (annotations added).
`See also SKH DDR4 Device Operation at 7.
`
`
`JEDEC DDR4 SDRAM Specification at 14 (annotations added).
`See also SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 7.
`
`
`
`
`
`
`Page 19 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 22 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`See, e.g., JEDEC DDR4 SDRAM Specification at 94.
`See also SKH DDR4 Device Operation at 97.
`
`
`
`
`Page 20 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 23 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`See, e.g., JEDEC DDR4 SDRAM Specification at 115.
`See also JEDEC DDR4 SDRAM Specification at 90-130.
`See also SKH DDR4 Device Operation at 126, 94-144.
`
`The SK hynix Products also include second edge connections for communicating address and control signals from the
`memory controller of the host system. For example, the SK hynix Products include the following input pins:
`
`
`
`
`
`
`Page 21 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 24 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`
`
`JEDEC LRDIMM Specification at 8.
`See also SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 6.
`
`
`
`
`See JEDEC RCD01 Specification at 63.
`
`
`Page 22 of 163
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 25 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`The PCB further includes an error edge connection in addition to the first set of edge connections and the second set of
`edge connections. For example, the SK hynix Products include the ALERT_n pin.
`
`
`JEDEC LRDIMM Specification at 30 (annotations added).
`
`
`
`
`Page 23 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 26 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`JEDEC LRDIMM Specification at 7 (annotations added).
`
`
`
`
`Page 24 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 27 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`JEDEC LRDIMM Specification at 9.
`
`
`
`
`Page 25 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 28 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a printed circuit board having edge connections that fit into a corresponding slot of the host system so as to be in electrical communication with the
`memory controller, the edge connections including first edge connections, second edge connections, and an error edge connection in addition to the first
`edge connections and the second edge connections;"
`
`
`JEDEC LRDIMM Specification at 11 (annotations added) (showing Alert_n at pin 208, separate and distinct from control,
`address, and data pins / edge connections).
`
`
`
`Page 26 of 163
`
`
`
`dynamic random access
`memory elements on the
`printed circuit board;
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 29 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`The SK hynix Products include dynamic random access memory elements on the printed circuit board.
`
`For example, the SK hynix Product includes a plurality of JEDEC-compliant synchronous dynamic random access
`memories (“SDRAMs”).
`
`
`See JEDEC LRDIMM Specification at 5 (annotations added).
`
`
`
`
`
`See SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 14 (showing SDRAM devices D0, D18, D5, and D23).
`
`Page 27 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 30 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`
`
`
`See SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 51.
`
`Specifically, the SK hynix HMA84GL7AMR4N-UHTE comprises 36 SDRAM components.
`
`
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE) (front side).
`
`
`
`
`Page 28 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 31 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE) (back side).
`
`
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE) (SDRAM).
`
`The SDRAM devices are JEDEC complaint.
`
`
`
`
`Page 29 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 32 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`
`JEDEC DDR4 SDRAM Specification at 1 (annotations added).
`See also SKH DDR4 Device Operation at 1.
`
`The SDRAM devices are outlined in red in the figure below.
`
`
`
`
`Page 30 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 33 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`
`JEDEC LRDIMM Specification at 17 (annotation added).
`See also SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 65.
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE) (front side).
`
`
`Page 31 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 34 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"dynamic random access memory elements on the printed circuit board;"
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE) (back side).
`
`
`
`
`
`Page 32 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 35 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`The SK hynix Products include a module controller on the printed circuit board and coupled to the dynamic random
`access memory elements, the module controller having an open drain output coupled to the error edge connection.
`
`The SK hynix Products comprise a module controller on the printed circuit board. For example, the SK hynix Products
`contain a JEDEC-compliant IDT 4RCD0124KC0 RCD on the printed circuit board.
`
`
`a module controller on the
`printed circuit board and
`coupled to the dynamic
`random access memory
`elements, the module
`controller having an open
`drain output coupled to the
`error edge connection; and
`
`See, e.g., JEDEC LRDIMM Specification at 12 (annotation added).
`
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 65 (annotations added).
`
`Specifically, the SK hynix Products contain a IDT 4RCD0124KC0 RCD.
`
`
`Page 33 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 36 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`
`
`(Exemplary Photo of SK Hynix HMA84GL7AMR4N-UHTE).
`
`The IDT 4RCD0124KC0 RCD is JEDEC Compliant.
`
`
`See 4RCD0124K DDR4 Register Clock Driver Webpage at 1.
`
`
`
`
`
`
`IDT Leader in Server Memory Chipsets at 1.
`
`Page 34 of 163
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 37 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`
`The SK hynix Products comprise a module controller coupled to the dynamic random access memory elements. For
`example, the IDT 4RCD0124KC0 RCD is coupled to the plurality of dynamic random access memory elements on the
`PCB.
`
`
`JEDEC LRDIMM Specification at 17.
`
`
`JEDEC LRDIMM Specification at 21.
`
`
`Page 35 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 38 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`See JEDEC RCD01 Specification at 63.
`
`
`
`
`Page 36 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 39 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`See JEDEC RCD01 Specification at 59 (annotations added).
`
`
`See JEDEC RCD01 Specification at 59.
`
`
`Page 37 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 40 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`See JEDEC RCD01 Specification at 60.
`
`
`
`
`Page 38 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 41 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 16.
`
`
`
`
`Page 39 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 42 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 14.
`
`The SK hynix Products comprise a module controller having an open drain output coupled to the error edge connection.
`For example, the JEDEC-complaint IDT 4RCD0124KC0 RCD contains an ALERT_n pin, which is an open drain output
`coupled to the error edge connection of the PCB.
`
`
`
`
`Page 40 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 43 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`See JEDEC RCD01 Specification at 60 (annotations added).
`
`
`
`
`Page 41 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 44 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`See JEDEC RCD01 Specification, at 144.
`
`
`
`
`Page 42 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 45 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`JEDEC LRDIMM Specification at 7 (annotations added).
`
`
`JEDEC LRDIMM Specification at 9 (annotations added).
`See also SKH HMA42GL7AFR4N / HMA84GL7AMR4N Datasheet at 5, 7.
`
`
`
`
`
`
`Page 43 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 46 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"a module controller on the printed circuit board and coupled to the dynamic random access memory elements, the module controller having an open drain
`output coupled to the error edge connection; and"
`
`JEDEC LRDIMM Specification at 30 (annotations added).
`
`
`JEDEC Annex D- Raw Card D for LRDIMM, at 20.
`
`
`
`Page 44 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 47 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module is operable in at least a first mode and a second mode, wherein the memory module in the first mode is configured to be
`trained with one or more training sequences;"
`The SK hynix Products are memory modules operable in at least a first mode and a second mode, wherein the memory
`module in the first mode is configured to be trained with one or more training sequences;.
`
`For example, the IDT 4RCD0124KC0 RCD is configured to operate in a first mode, e.g., Clock-to-CA training mode
`(e.g., when RC0C control word = x001).
`
`
`wherein the memory module
`is operable in at least a first
`mode and a second mode,
`wherein the memory module
`in the first mode is
`configured to be trained with
`one or more training
`sequences;
`
`See JEDEC RCD01 Specification at 72 (annotations added).
`
`For example, the IDT 4RCD0124KC0 RCD is configured to operate in a second mode, e.g., a normal operating mode
`(e.g., when RC0C control word = x000).
`
`
`
`
`Page 45 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 48 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module is operable in at least a first mode and a second mode, wherein the memory module in the first mode is configured to be
`trained with one or more training sequences;"
`
`See JEDEC RCD01 Specification at 72 (annotations added).
`
`The SK hynix Products in the first mode, e.g., Clock-to-CA training mode, are configured to be trained with one or more
`training sequences. For example, the SK hynix Products execute a series of training sequences during Clock-to-CA
`training mode
`
`
`
`
`
`
`
`
`
`Page 46 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 49 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module is operable in at least a first mode and a second mode, wherein the memory module in the first mode is configured to be
`trained with one or more training sequences;"
`
`See JEDEC RCD01 Specification at 54.
`
`
`
`
`Page 47 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 50 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module is operable in at least a first mode and a second mode, wherein the memory module in the first mode is configured to be
`trained with one or more training sequences;"
`
`See JEDEC RCD01 Specification at 54.
`
`
`
`
`
`Page 48 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 51 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module in the second mode is configured to perform one or more memory read or write operations not associated with the one or
`more training sequences by communicating data signals via the first edge connections in response to address and command signals received via the second
`edge connections;"
`The SK hynix Products in the second mode are configured to perform one or more memory read or write operations not
`associated with the one or more training sequences by communicating data signals via the first edge connections in
`response to address and command signals received via the second edge connections.
`
`For example, the SK hynix Products are configured to operate in a normal operating mode, e.g., a second mode.
`
`
`wherein the memory module
`in the second mode is
`configured to perform one or
`more memory read or write
`operations not associated
`with the one or more training
`sequences by
`communicating data signals
`via the first edge connections
`in response to address and
`command signals received
`via the second edge
`connections;
`
`See JEDEC RCD01 Specification at 72 (annotations added).
`
`The SK hynix Products are configured to perform one or more memory read or write operations not associated with the
`one or more training sequences by communicating data signals via the first edge connections in response to address and
`command signals received via the second edge connections.
`
`For example, during the second mode (e.g., a normal mode of operation), the RCD receives address and control signals
`corresponding to read and write commands from the memory controller via the second edge connections. The RCD
`outputs corresponding address and control signals to the SDRAM devices, which cause the SDRAM devices to execute
`read and write operations.
`
`
`
`Page 49 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 52 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module in the second mode is configured to perform one or more memory read or write operations not associated with the one or
`more training sequences by communicating data signals via the first edge connections in response to address and command signals received via the second
`edge connections;"
`
`See JEDEC RCD01 Specification at 63.
`
`
`
`
`Page 50 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 53 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module in the second mode is configured to perform one or more memory read or write operations not associated with the one or
`more training sequences by communicating data signals via the first edge connections in response to address and command signals received via the second
`edge connections;"
`
`See JEDEC RCD01 Specification at 59 (annotations added).
`
`
`See JEDEC RCD01 Specification at 59.
`
`
`Page 51 of 163
`
`
`
`
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 54 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module in the second mode is configured to perform one or more memory read or write operations not associated with the one or
`more training sequences by communicating data signals via the first edge connections in response to address and command signals received via the second
`edge connections;"
`
`See JEDEC RCD01 Specification at 60.
`
`
`
`
`Page 52 of 163
`
`
`
`Case 6:20-cv-00194-ADA Document 1-5 Filed 03/17/20 Page 55 of 165
`
`U.S. Patent No. 9,858,218: Claim 1
`"wherein the memory module in the second mode is configured to perform one or more memory read or write operations not associated with the one or
`more training sequences by communicating data signals via the first edge connections in response to address and command signals received via the second
`edge connections;"
`
`SKH HMA42GL7
Accessing this document will incur an additional charge of $.
After purchase, you can access this document again without charge.
Accept $ Charge
Still Working On It
This document is taking longer than usual to download. This can happen if we need to contact the court directly to obtain the document and their servers are running slowly.
Give it another minute or two to complete, and then try the refresh button.
A few More Minutes ... Still Working
It can take up to 5 minutes for us to download a document if the court servers are running slowly.
Thank you for your continued patience.
This document could not be displayed.
We could not find this document within its docket. Please go back to the docket page and check the link. If that does not work, go back to the docket and refresh it to pull the newest information.
Your account does not support viewing this document.
You need a Paid Account to view this document. Click here to change your account type.
Your account does not support viewing this document.
Set your membership
status to view this document.
With a Docket Alarm membership, you'll
get a whole lot more, including:
- Up-to-date information for this case.
- Email alerts whenever there is an update.
- Full text search for other cases.
- Get email alerts whenever a new case matches your search.
One Moment Please
The filing “” is large (MB) and is being downloaded.
Please refresh this page in a few minutes to see if the filing has been downloaded. The filing will also be emailed to you when the download completes.
Your document is on its way!
If you do not receive the document in five minutes, contact support at support@docketalarm.com.
Sealed Document
We are unable to display this document, it may be under a court ordered seal.
If you have proper credentials to access the file, you may proceed directly to the court's system using your government issued username and password.
Access Government Site
