Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 1 of 24
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` Exhibit 1
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`case 6:21-cv-oozas-ADA DocumeHIIlllllllllHlIlllflIlllllllllllllllllllvllllflllllillflllllllllll||||||||
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 2 of 24
`US006317804B1
`
`(12) United States Patent
`US 6,317,804 B1
`(10) Patent N0.:
`(45) Date of Patent:
`Nov. 13, 2001
`Levy et al.
`
`(54)
`
`(75)
`
`(73)
`
`CONCURRENT SERIAL INTERCONNECT
`
`FOR INTEGRATING FUNCTIONAL BLOCKS
`IN AN INTEGRATED CIRCUIT DEVICE
`
`Inventors: Paul S. Levy, Chandler; Judson Alan
`Lehman Scottsdale both OfAZ (US)
`’
`’
`.
`.
`.
`.
`ASSIgnee~ Phlhps semlc‘mducwrs Inc” New
`York, NY (US)
`
`5,754,828 *
`
`5/1998 Adan et a1.
`.......................... 395/500
`
`5,838,937 * 11/1998 Lee et a1.
`.. 710/131
`5,870,310
`2/1999 Malladl
`..
`364/490
`3/2000 Lee ................
`6,035,345 *
`710/8
`
`
`6’035’414 *
`714/7
`3/2000 Okaz‘lwa et al'
`‘
`
`6,041,400
`3/2000 Ozcellk et a1. ............. 712/35
`6,094,436 *
`................... 370/420
`7/2000 Runaldue et a1.
`6,112,241 *
`8/2000 Abdelnour et a1.
`.................. 709/224
`
`6,138,185 * 10/2000 Nelson etal. .............. 710/33
`6,145,024 * 11/2000 Maezawa et al.
`..................... 710/14
`
`Notice:
`
`Subject to any disclaimer, the term of this
`patent ls extended or adjusted under 35
`U~S~C~ 154(b) by 0 days
`
`FOREIGN PATENT DOCUMENTS
`0 308 890 A2
`3/1989 (EP) .
`0 653 896 A2
`5/1995 (EP) .
`
`(21)
`
`Appl. N0.: 09/201,450
`
`(22)
`
`Filed:
`
`NOV_ 30, 1998
`
`(51)
`(52)
`(58)
`
`(56)
`
`Int. Cl.7 ............................. G06F 13/00; G06F 13/14
`US. Cl.
`............................................. 710/129; 710/126
`Field of Search ..................................... 710/129—132,
`71038; 709/252—253; 370/360_385’ 498—545
`.
`References Cited
`
`* cited by examiner
`
`Primary Examiner—Sumati Lefkowitz
`(74) Attorney, Agent, or Firm—Wood, Herron & Evans,
`L.L.P.
`
`ABSTRACT
`(57)
`A circuit arrangement and method interface multiple func-
`tional blocks Within an integrated circuit device via a
`.
`.
`.
`concurrent serlal lnterconnect capable of routlng separate
`serial command, data and clock signals between functional
`blocks in the device. The concurrent serial interconnect
`utilizes a plurality of serial ports that are selectively coupled
`-
`to on: “.101?” by an.ln:8rfacflc°m1r°tl)letr to difine one or
`more oglca communlca 1011C annes eween vvo or more
`of the serlal ports. Each serlal port ls coupled Vla a pomt-
`to-point interconnection With a port interface in a functional
`block. In addition, the concurrent serial interconnect facili-
`tates the design of an integrated circuit device by supporting
`the addition of a serial interconnect to an assemblage of
`functional blocks, With each functional block associated
`With one of a plurality of serial ports in the serial intercon-
`nect
`'
`
`us. PATENT DOCUMENTS
`.
`13133: 120mm? ““““““““““““““““ 333/322
`3922113923:
`grawa ...............................
`,
`,
`2/1993 Niehaus et al.
`...................... 370/248
`5,189,665 *
`.. 710/132
`5,261,059 * “/1993 Hedberg et a1.
`
`.
`.. 364/754
`5 311 459
`5/1994 D’Luna et a1.
`...... 710/129
`5,428,750 4
`6/1995 Hsieh et a1.
`
`..... 340/825.79
`5,430,442 *
`7/1995 Kaiser et a1.
`
`11/1995 Vanbuskirk et a1.
`..... 395/200.01
`5,469,545
`
`...... 395/800
`5,513,369
`4/1996 Patel et a1.
`
`55377583 :
`7/1996 Truong
`713/500
`
`575557540
`9/1996 Radke ‘1""""""
`370/462
`
`.. 709/209
`5,555,543 *
`9/1996 Grohoskl et a1.
`...... 370/360
`5,604,735 *
`2/1997 Levinson et a1.
`
`
`5,655,142
`8/1997 Gephardt et a1.
`. 395/800.32
`5,680,402 * 10/1997 Olnowich et a1.
`................... 370/498
`
`
`40 Claims, 9 Drawing Sheets
`
`24
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 3 of 24
`Case 6:21-cv-00263-ADA Document 1—1 Filed 03/16/21 Page 3 of 24
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`US. Patent
`
`Nov. 13, 2001
`
`Sheet 1 0f 9
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`US 6,317,804 B1
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 4 of 24
`Case 6:21-cv-00263-ADA Document 1—1 Filed 03/16/21 Page 4 of 24
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`US. Patent
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`Nov. 13, 2001
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`Sheet 2 0f 9
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`US 6,317,804 B1
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 5 of 24
`Case 6:21-cv-00263-ADA Document 1—1 Filed 03/16/21 Page 5 of 24
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`US. Patent
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`Nov. 13, 2001
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`Sheet 3 0f 9
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`US 6,317,804 B1
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 6 of 24
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 6 of 24
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`US. Patent
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`Nov. 13, 2001
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`Sheet 4 0f 9
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`US 6,317,804 B1
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 7 of 24
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 7 of 24
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 8 of 24
`Case 6:21-cv-00263-ADA Document 1—1 Filed 03/16/21 Page 8 of 24
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`US. Patent
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`Nov. 13, 2001
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`Sheet 6 0f 9
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`US 6,317,804 B1
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 9 of 24
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 10 of 24
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 11 of 24
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`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 12 of 24
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 12 of 24
`
`US 6,317,804 B1
`
`1
`CONCURRENT SERIAL INTERCONNECT
`FOR INTEGRATING FUNCTIONAL BLOCKS
`IN AN INTEGRATED CIRCUIT DEVICE
`
`FIELD OF THE INVENTION
`
`The invention is generally related to integrated circuit
`device design and architecture, and in particular,
`to an
`interface for interconnecting multiple functional blocks
`together in an integrated circuit device.
`BACKGROUND OF THE INVENTION
`
`Computer technology has advanced a great deal over the
`last several decades. Whereas computers once filled entire
`rooms, and were constructed using individually packaged
`transistors and/or vacuum tubes to perform different logical
`functions,
`innovations in semiconductor manufacturing
`techniques have enabled multiple transistors, or logic gates,
`to be integrated together on a single integrated circuit
`device, or “chip” to perform a greater number of logical
`functions. The size and number of logic gates that can be
`integrated together on a chip continues to improve, and
`whereas early chips had at most only a few hundred gates,
`more recent chips have been developed that incorporate
`more on the order of millions of gates. Furthermore,
`advances in integration have permitted designs that were at
`one time implemented using multiple chips to be imple-
`mented in a single chip.
`the
`As chip designs become more complex, however,
`design and development process becomes more expensive
`and time consuming. To alleviate this difficulty, design tools
`have been developed that enable developers to build custom
`chips by assembling together smaller, generic components
`that perform basic functions required for the design. By
`using generic components, design time and effort are
`reduced, since circuits do not need to be designed gate by
`gate. Moreover, the components usually can be tested and
`optimized prior to assembly in a particular design, so that the
`testing effort placed on the developer of an overall design is
`substantially reduced.
`The ability to integrate greater numbers of gates onto a
`chip has also permitted the complexity of the generic
`components used by design tools to increase. Whereas early
`generic components replicated basic functions such as
`multiplexers, registers, counters, etc., more advanced com-
`ponents typically replicate higher level functions such as
`that of microprocessors, memory controllers, communica-
`tions interface controllers, etc. These more advanced com-
`ponents are referred to herein as functional blocks, insofar as
`they are configured to perform one or more high level
`functions in a design. Functional blocks typically are por-
`table to the extent that they are reusable in different designs.
`Moreover, they are often autonomous, and thus capable of
`operating independently and concurrently with other com-
`ponents in a design.
`One difficulty associated with the use of components such
`as functional blocks arises from the need for the various
`
`components in a design to communicate with and transfer
`information among one another. Each component typically
`has one or more interfaces defined therefor through which
`communication with other components, or with other
`devices external to a chip, is handled. These interfaces are
`typically interconnected with one another over an intercon-
`nect system such as a bus to support communication
`between the different components.
`For example, one common manner of interconnecting
`multiple components is through the use of a multidrop bus.
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`With a multi-drop bus, each component is coupled to a
`common set of lines, so that each component is capable of
`receiving every communication passed over the bus. Infor-
`mation passed over a bus is usually associated with a
`particular address or other identifier so that, only the com-
`ponent that is the target of the information actually receives
`and processes that information. The other components that
`are not targeted for the information ignore the information.
`Typically, a bus is parallel, incorporating multiple lines so
`that multiple bits of information can be transmitted simul-
`taneously. Moreover, both control information, used by one
`component to control the operation of another component,
`and data, representing the information being manipulated by
`the components, are typically sent over the same lines in the
`bus. For example, one bus architecture used in integrating
`multiple functional blocks in a chip is the Peripheral Com-
`ponent Interconnect (PCI) bus architecture, which is more
`conventionally used at
`the board level to interconnect a
`microprocessor with different peripheral devices in a com-
`puter.
`However, bus-type interconnections suffer from a number
`of drawbacks that limit their usefulness in interconnecting
`multiple functional blocks in a chip. First, parallel bus
`architectures require a relatively large number of lines, or
`wires, to run between the various components connected to
`the bus. Routing wires between components can take up
`valuable space in a design and reduce the number of
`components that can fit into the design. Many parallel buses,
`for example, transmit data in 32- or 64-bit words, requiring
`at a minimum 32 or 64 lines to be routed to each component,
`not counting any additional control signals that may be
`required.
`Second, typically only one component can transmit infor-
`mation over a parallel bus at a time. Therefore, other
`components that desire to transmit information typically
`must wait until
`that component
`is done transmitting its
`information, or in the alternative, each component must
`share the bus and transmit pieces of information one after
`another, which slows down the transmission rate for all
`components. Also, control information and data typically
`share the same lines in a parallel bus, and as a result, control
`operations that might otherwise be capable of being per-
`formed within a particular component without requiring
`access to the bus may have to wait until a data transmission,
`started prior to the desired control operation, is complete.
`Third, the overall speed of a parallel bus may be limited,
`and thus limit the potential bandwidth of information that
`can be communicated between components. Bandwidth in a
`parallel bus is typically improved by increasing the width of
`the bus or increasing the clock speed of the bus. Increasing
`the width, however, adds additional lines to the bus, thus
`adding to the routing density of the design. Increasing the
`clock speed, on the other hand, may limit the number of
`components that can be attached to the bus, since the number
`of components can affect the amount of load and routing
`parasitics on the bus, each of which limits permissible clock
`speed.
`Therefore, a significant need exists in the art for an
`improved manner of interconnecting components such as
`functional blocks and the like in an integrated circuit design,
`and in particular, for a manner of interconnecting compo-
`nents that is more flexible, compact, fast, reusable, and
`expandible than conventional designs.
`SUMMARY OF THE INVENTION
`
`The invention addresses these and other problems asso-
`ciated with the prior art by providing a circuit arrangement
`
`

`

`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 13 of 24
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 13 of 24
`
`US 6,317,804 B1
`
`3
`and method that interface multiple functional blocks within
`an integrated circuit device via a concurrent serial intercon-
`nect that is capable of routing separate serial command, data
`and clock signals between functional blocks in the device. A
`concurrent serial interconnect consistent with the invention
`
`utilizes a plurality of serial ports that are selectively coupled
`to one another by an interface controller to define one or
`more logical communication channels between two or more
`of the serial ports. The logical communication channels in
`essence function as point-to-point serial interconnections
`between functional blocks, so that direct communications
`between logically connected functional blocks can occur.
`Through the use of serial interconnects, the number of
`lines required to be routed to and from individual functional
`blocks is reduced, thereby simplifying the integration of
`functional blocks into a design and reducing the routing
`congestion associated with inter-block communication. In
`addition, by communicating via separate serial command,
`data and clock signals, high speed data throughput can be
`supported. Furthermore, should more than one logical com-
`munication channel be supported by an interface controller
`consistent with the invention, multiple communication ses-
`sions can occur in parallel, thereby further increasing overall
`data throughput.
`Another benefit of a concurrent serial interconnect con-
`
`sistent with the invention is that the design of integrated
`circuit devices and the like is substantially simplified. Func-
`tional blocks may be assembled together through the addi-
`tion of a serial interconnect, with each functional block
`associated with one of a plurality of serial ports in the serial
`interconnect by routing separate serial command, data and
`clock wires therebetween. Design and development is sim-
`plified as the addition of new functional blocks to a design
`typically affects only the design of the serial interconnect,
`and specifically,
`the interface controller used therein.
`Moreover, modular testing and verification is facilitated
`insofar as communications between functional blocks pri-
`marily passes through the serial interconnect, and the need
`for
`testing and verifying individual
`interconnections
`between functional blocks is often reduced or eliminated.
`
`These and other advantages and features, which charac-
`terize the invention, are set forth in the claims annexed
`hereto and forming a further part hereof However, for a
`better understanding of the invention, and of the advantages
`and objectives attained through its use, reference should be
`made to the Drawings, and to the accompanying descriptive
`matter, in which there is described exemplary embodiments
`of the invention.
`
`BRIEF DESCRIPTION OF THE DRAWINGS
`
`FIG. 1 is a block diagram of a circuit arrangement for an
`integrated circuit device consistent with the invention.
`FIG. 2 is a block diagram of the interface controller in the
`circuit arrangement of FIG. 1.
`FIG. 3 is a block diagram of a three channel implemen-
`tation of the interface controller of FIG. 2.
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`FIG. 4 is a flowchart illustrating the sequence of opera-
`tions performed during a system reset by the interface
`controller of FIG. 2.
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`FIG. 5 is a flowchart illustrating a sequence of operations
`performed when establishing a logical communication chan-
`nel in the circuit arrangement of FIG. 1.
`FIG. 6 is a flowchart illustrating a sequence of operations
`performed when releasing a logical communication channel
`in the circuit arrangement of FIG. 1.
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`FIGS. 7A, 7B and 7C are timing diagrams respectively
`illustrating exemplary data stream transmissions between
`two ports during establishment of a logical channel, pro-
`cessing of a read request over the established channel, and
`release of the channel.
`
`FIG. 8 is a flowchart illustrating a sequence of operations
`performed during an implicit preemption operation for the
`circuit arrangement of FIG. 1.
`FIG. 9 is a flowchart illustrating a sequence of operations
`performed during an explicit preemption operation for the
`circuit arrangement of FIG. 1.
`FIG. 10 is a block diagram of the primary logic compo-
`nents in a functional block circuit arrangement consistent
`with the invention.
`
`FIG. 11 is a block diagram of a development environment
`data processing system consistent with the invention.
`FIG. 12 is a block diagram of the system controller in the
`development environment data processing system of FIG.
`11.
`
`FIG. 13 is a block diagram of a set top box data processing
`system consistent with the invention.
`FIG. 14 is a block diagram of the set top box controller in
`the set top box data processing system of FIG. 13.
`
`DETAILED DESCRIPTION
`
`The illustrated embodiments of the invention generally
`rely on a concurrent serial interconnect to interface a plu-
`rality of functional blocks together in an integrated circuit
`device circuit arrangement. A concurrent serial interconnect
`consistent with the invention includes a plurality of serial
`ports under the control of an interface controller, and
`coupled via a plurality of direct point-to-point serial inter-
`connects to different functional blocks in the circuit arrange-
`ment. The interface controller selectively couples serial
`ports together to define one or more logical communications
`channels through which information is passed by the func-
`tional blocks associated with the coupled serial ports.
`Afunctional block may be considered to include any logic
`circuitry configured to perform one or more high level
`functions in an integrated circuit device design. Most func-
`tional blocks are “portable”, whereby they are reusable in
`different designs. Moreover, many functional blocks are also
`“autonomous”, and thus capable of operating independently
`and concurrently with other components in a design.
`Examples of functional blocks include, but are not limited to
`processors, controllers, external
`interfaces, encoders,
`decoders, signal processors, and any other analog and/or
`digital circuitry performing a particular function or set of
`functions. Often, functional blocks are designed, developed
`and verified as independent entities, and may even be
`obtained from third parties, rather than the designers of the
`overall integrated circuit device.
`The integration of multiple functional blocks via a con-
`current serial interconnect consistent with the invention is
`
`typically implemented in a circuit arrangement for a pro-
`cessor or other programmable integrated circuit device, and
`it should be appreciated that a wide variety of programmable
`devices may utilize the various features disclosed herein.
`Moreover, as is well known in the art, integrated circuit
`devices are typically designed and fabricated using one or
`more computer data files, referred to herein as hardware
`definition programs, that define the layout of the circuit
`arrangements on the devices. The programs are typically
`generated by a design tool and are subsequently used during
`manufacturing to create the layout masks that define the
`
`

`

`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 14 of 24
`Case 6:21-cv-00263-ADA Document 1-1 Filed 03/16/21 Page 14 of 24
`
`US 6,317,804 B1
`
`5
`circuit arrangements applied to a semiconductor wafer.
`Typically, the programs are provided in a predefined format
`using a hardware definition language (HDL) such as VHDL,
`verilog, EDIF, etc. While the invention has and hereinafter
`will be described in the context of circuit arrangements
`implemented in fully functioning integrated circuit devices
`and data processing systems utilizing such devices, those
`skilled in the art will appreciate that circuit arrangements
`consistent with the invention are capable of being distributed
`as program products in a variety of forms, and that the
`invention applies equally regardless of the particular type of
`signal bearing media used to actually carry out the distri-
`bution. Examples of signal bearing media include but are not
`limited to recordable type media such as volatile and non-
`volatile memory devices, floppy disks, hard disk drives,
`CD-ROM’s, and DVD’s, among others and transmission
`type media such as digital and analog communications links.
`Turning now to the Drawings, wherein like numbers
`denote like parts throughout
`the several views, FIG. 1
`illustrates a representative integrated circuit device circuit
`arrangement 10 consistent with the invention. A concurrent
`serial interconnect 12, including an interface controller 14,
`is used to interface a host 20 with a plurality of functional
`blocks 22, 24, 26 and 28 (also denoted as FB 1 .
`.
`. n). Host
`20 may also be considered as a functional block that has, in
`addition to any other high level functionality defined
`therefor, further logic circuitry to operate as a master device
`for concurrent serial interconnect 12.
`
`Each functional block 20, 22, 24, 26 and 28 includes a
`respective port interface 30, 32, 34, 26 and 38 that interfaces
`with a plurality of serial ports 40, 42, 44, 46 and 48 (also
`denoted as Ports 0.
`.
`. n) over direct point-to-point serial
`interconnections 50, 52, 54, 56 and 58. Each serial port
`40—48 is under the control of interface controller 14 to
`
`selectively define one or more logical communication chan-
`nels between two or more functional blocks 20—28.
`
`Moreover, with host 20 functioning as the master for inter-
`connect 12, port 40 defines a master port
`for
`the
`interconnect,
`through which initialization information is
`provided by the host.
`Each serial interconnection 50—58 includes separate serial
`command, data and clock lines. The serial command lines
`are used to transmit serial encoded command & control
`information between functional blocks or between the inter-
`face controller and a functional block. The serial data lines
`are used to transmit serial encoded data between functional
`blocks or between the interface controller and a functional
`
`block, with the data lines further used to provide additional
`information for the various commands transmitted over the
`
`serial command lines, as will be outlined in greater detail
`below. The serial data is framed by the serial command
`information.
`
`The serial clock lines are used to transmit clock signals to
`synchronize the command and data lines, thereby permitting
`the functional blocks to operate substantially asynchro-
`nously from one another and/or from the interface controller,
`if desired. In the alternative, the functional blocks may be
`synchronized by the same distributed clock signal. The
`command and data lines may be double edge or single edge
`clocked as desired.
`
`Each such line may be implemented in a number of
`manners. For example, each line may be implemented using
`a bidirectional wire, or a pair of unidirectional wires may be
`provided to support concurrent communication in both
`directions between a serial port and its associated functional
`block. In addition, lines may be implemented with single-
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`ended wires, or may be implemented by differential pairs of
`wires to improve performance. In the implementation dis-
`cussed hereinafter, for example, differential wire pairs are
`provided for each of command in, data in and clock in
`signals (from a functional block to a serial port), as well as
`for each of command out, data out, and clock out signals
`(from a serial port to a functional block), resulting in a total
`of only 12 lines for each serial interconnection 50—58.
`In addition, as shown by line 60, each functional block
`may or may not provide external input and/or output for the
`integrated circuit device, as dictated by the particular design
`of the functional block.
`
`As shown in FIG. 2, interface controller 14 includes a
`matrix controller 64 interfaced with a connector matrix 66.
`
`The matrix controller is also interfaced with a memory
`storage device 67 within which arbitration data, defining an
`arbitration scheme for the controller,
`is stored. A set of
`matrix control lines 68 are output by controller 64 to control
`the configuration of matrix 66 based upon the defined
`arbitration scheme for the controller. In addition, matrix 66
`receives the command/data/clock signals from each of serial
`ports 40, 42, 44, 46 and 48, represented by lines 70, 72, 74,
`76 and 78, respectively. The serial lines for each serial port
`are also provided to matrix controller 64 to permit
`the
`controller to decode commands passed thereto over the
`respective serial lines from a particular port so that the
`matrix controller can reconfigure the matrix as necessary to
`establish the desired logical communications channel(s)
`between selected ports.
`The configuration of both matrix controller 64 and con-
`nector matrix 66 can vary significantly based upon the
`desired connectivity between the various functional blocks.
`Any number of known switch matrix implementations may
`be used, including cross-bar switches, tree structures, etc.
`Furthermore, a connector matrix may be developed to sup-
`port any number of concurrent
`logical communications
`channels. Moreover, in some implementations,
`it may be
`desirable to split the input and output lines between ports to
`permit one port to receive information from one channel, yet
`transmit information on another channel.
`
`For example, FIG. 3 illustrates one suitable implementa-
`tion of connector matrix 66 as a three channel cross-bar
`
`interconnect for in connecting five serial ports 40—48 (Ports
`0 .
`.
`. 4). To control matrix 66, matrix controller 64 includes
`three logic blocks: a route command & control block 80; a
`route request block 82; and a channel matrix control block
`84.
`
`Connector matrix 66 has three channels 86, 88, 90 defined
`therein for selectively coupling together ports 40—48. For
`illustrative purposes, each port 40—48 is represented at two
`positions in the figure, with the left representation repre-
`sent